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? 2011 freescale semiconductor, inc. all rights reserved. freescale semiconductor technical data this document provides an overview of the mpc8358e powerquicc ii pro processor revision 2.1 pbga features, including a block diagram showing the major functional components. this device is a cost-effective, highly integrated communications processor that addresses the needs of the networking, wireless infrastructure, and telecommunications markets. target applications include next generation dslams, network interface cards for 3g base stations (node bs), routers, media gateways, and high end iads. the device extends current powerquicc ii pro offerings, adding higher cpu performance, additional functionality, faster interfaces, and robust interworking between protocols while addres sing the requirements related to time-to-market, price, power, and package size. this device can be used for the control plane and also has data plane functionality. for functional characteristics of the processor, refer to the mpc8360e powerquicc ii pro integrated communications processor family reference manual , rev. 3. to locate any updates for this document, refer to the mpc8360e product summary page on our website listed on the back cover of this document or contact your freescale sales office. document number: mpc8358eec rev. 3, 01/2011 contents 1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. electrical characteristics . . . . . . . . . . . . . . . . . . 7 3. power characteristics . . . . . . . . . . . . . . . . . . . 12 4. clock input timing . . . . . . . . . . . . . . . . . . . . . 13 5. reset initialization . . . . . . . . . . . . . . . . . . . . 15 6. ddr and ddr2 sdram . . . . . . . . . . . . . . . . 18 7. duart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8. ucc ethernet controller: three-speed ethernet, mii management . . . . . . . . . . . . . . . . . . . . . . . 25 9. local bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10. jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 11. i 2 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12. pci . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13. timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 14. gpio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 15. ipic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 16. spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 17. tdm/si . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 18. utopia/pos . . . . . . . . . . . . . . . . . . . . . . . . . 59 19. hdlc, bisync, transparent, and synchronous uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 20. usb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 21. package and pin listings . . . . . . . . . . . . . . . . . 65 22. clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 23. thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 24. system design information . . . . . . . . . . . . . . . 89 25. ordering information . . . . . . . . . . . . . . . . . . . . 92 26. document revision history . . . . . . . . . . . . . . 94 mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 2 freescale semiconductor overview 1overview this section describes a high-leve l overview including features and general operation of the mpc8358e powerquicc ii pro processor. a major component of this device is the e300 core, which includes 32 kbytes of instruction and data cache and is fu lly compatible with the power architecture? 603e instruction set. the new quicc engine module pr ovides termination, interworking, and switching between a wide range of protocols including atm, ethernet, hdlc, and pos. the quicc engine module?s enhanced interworking eases the transition and reduces investment costs from atm to ip based systems. the mpc8358e has a single ddr sdram memory controller. the mpc8358e also offers a 32-bit pci controller, a flexible local bus, and a dedicated security engine. figure 1 shows the mpc8358e block diagram. figure 1. mpc8358e block diagram major features of the mpc8358e are as follows: ? e300 powerpc processor core (enhanced version of the mpc603e core) ? operates at up to 400 mhz (for the mpc8358e) ? high-performance, superscalar processor core ? floating-point, integer, load/store, system register, and branch processing units memory controllers gpcm/upm/sdram 32/64 ddr interface unit pci bridge local bus bus arbitration duart dual i2c 4 channel dma interrupt controller protection & configuration system reset clock synthesizer system interface unit (siu) local baud rate generators multi-user ram ucc8 parallel i/o accelerators dual 32-bit risc cp serial dma & 2 virtual dmas 2 gmii/ rgmii/tbi/rtbi 6 mii/ rmii 4 tdm ports 1 utopia/pos (31/124 mphy) serial interface quicc engine module jtag/cop power management timers fpu classic g2 mmus 32kb d-cache 32kb i-cache security engine e300 core pci ddrc ucc5 ucc4 ucc3 ucc2 ucc1 usb spi2 time slot assigner spi1
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 freescale semiconductor 3 overview ? 32-kbyte instruction cache, 32-kbyte data cache ? lockable portion of l1 cache ? dynamic power management ? software-compatible with the freescale processor families implementing the power architecture? technology ? quicc engine unit ? two 32-bit risc controllers for flexible support of the communications peripherals, each operating up to 400 mhz (for the mpc8358e) ? serial dma channel for receive and transmit on all serial channels ? quicc engine module peripheral request interface (for sec, pci, ieee std. 1588?) ? six uccs on the mpc8358e supporting the following protocols and interfaces (not all of them simultaneously): ? ieee 1588 protocol supported ? 10/100 mbps ethernet/ieee std. 802.3? cdma/cs interface through a media-independent interface (mii, rmii, rgmii) 1 ? 1000 mbps ethernet/ieee 802.3 cdma/cs interface through a media-independent interface (gmii, rgmii, tbi, rtbi) on ucc1 and ucc2 ? 9.6-kbyte jumbo frames ? atm full-duplex sar, up to 622 mbps (oc-12/stm-4), aal0, aal1, and aal5 in accordance itu-t i.363.5 ? atm aal2 cps, sssar, and ssted up to 155 mbps (oc-3/stm-1) mbps full duplex (with 4 cps packets per cell) in accordance itu-t i.366.1 and i.363.2 ? atm traffic shaping for cbr, vbr, ubr, and gfr traffic types compatible with atm forum tm4.1 for up to 64-kbyte simultaneous atm channels ? atm aal1 structured and unstructured circuit emulation service (ces 2.0) in accordance with itu-t i.163.1 and atm forum af-vtoa-00-0078.000 ? ima (inverse multiplexing over atm) for up to 31 ima links over 8 ima groups in accordance with the atm forum af-phy-0086.000 (version 1.0) and af-phy-0086.001 (version 1.1) ? atm transmission convergence layer support in accordance with itu-t i.432 ? atm oam handling features compatible with itu-t i.610 ? ppp, multi-link (ml-ppp), multi-class (mc-ppp) and ppp mux in accordance with the following rfcs: 1661, 1662, 1990, 2686, and 3153 ? ip support for ipv4 packets including tos, ttl, and header checksum processing ? ethernet over first mile ieee 802.3ah ? shim header ? ethernet-to-ethernet/aal5/aal2 inter-working ? l2 ethernet switching using mac address or ieee std. 802.1p/q? vlan tags 1.smii or sgmii media-independent interface is not currently supported.
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 4 freescale semiconductor overview ? atm (aal2/aal5) to ethernet (ip) interworking in accordance with rfc2684 including bridging of atm ports to ethernet ports ? extensive support for atm statistics and ethernet rmon/mib statistics ? aal2 protocol rate up to 4 cps at oc-3/stm-1 rate ? packet over sonet (pos) up to 622-mbps full-duplex 124 multiphy ? pos hardware; microcode must be loaded as an iram package ? transparent up to 70-mbps full-duplex ? hdlc up to 70-mbps full-duplex ? hdlc bus up to 10 mbps ? asynchronous hdlc ? uart ? bisync up to 2 mbps ? user-programmable virtual fifo size ? quicc multichannel controlle r (qmc) for 64 tdm channels ? one utopia/pos interface on the mpc8358e supporting 31/124 multiphy ? two serial peripheral interfaces (spi); sp i2 is dedicated to ethernet phy management ? four tdm interfaces on the mpc8358e with 1-bit mode for e3/t3 rates in clear channel ? sixteen independent baud rate generators and 30 input clock pins for supplying clocks to ucc serial channels ? four independent 16-bit timers that can be interconnected as four 32-bit timers ? interworking functionality: ? layer 2 10/100-base t ethernet switch ? atm-to-atm switching (aal0, 2, 5) ? ethernet-to-atm switching with l3/l4 support ? ppp interworking ? security engine is optimized to handle all the algorithms associated with ipsec, ssl/tls, srtp, 802.11i?, iscsi, and ike processing. the security engine contains four crypto-channels, a controller, and a set of crypto execution units (eus). ? public key execution unit (pkeu) supporting the following: ? rsa and diffie-hellman ? programmable field size up to 2048 bits ? elliptic curve cryptography ? f2m and f(p) modes ? programmable field size up to 511 bits ? data encryption standard execution unit (deu) ?des, 3des ? two key (k1, k2) or three key (k1, k2, k3) ? ecb and cbc modes for both des and 3des
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 freescale semiconductor 5 overview ? advanced encryption standard unit (aesu) ? implements the rinjdael symmetric key cipher ? key lengths of 128, 192, and 256 bits, two key ? ecb, cbc, ccm, and counter modes ? arc four execution unit (afeu) ? implements a stream cipher compatible with the rc4 algorithm ? 40- to 128-bit programmable key ? message digest execution unit (mdeu) ? sha with 160-, 224-, or 256-bit message digest ? md5 with 128-bit message digest ? hmac with either sha or md5 algorithm ? random number generator (rng) ? four crypto-channels, each supporting multi-command descriptor chains ? static and/or dynamic assignment of crypto-ex ecution units via an integrated controller ? buffer size of 256 bytes for each execution unit, with flow control for large data sizes ? storage/nas xor parity generation accelerator for raid applications ? ddr sdram memory controller on the mpc8358e ? programmable timing supporting both ddr1 and ddr2 sdram ? on the mpc8358e, the ddr bus can be configured as a 32- or 64-bit bus ? 32- or 64-bit data interface, up to 266 mhz (for the mpc8358e) data rate ? four banks of memory, each up to 1 gbyte ? dram chip configurations from 64 mbits to 1 gigabit with 8/16 data ports ? full ecc support ? page mode support (up to 16 simultaneous ope n pages for ddr1, up to 32 simultaneous open pages for ddr2) ? contiguous or discontiguous memory mapping ? read-modify-write support ? sleep mode support for self refresh sdram ? supports auto refreshing ? supports source clock mode ? on-the-fly power management using cke ? registered dimm support ? 2.5-v sstl2 compatible i/o for ddr1, 1.8-v sstl2 compatible i/o for ddr2 ? external driver impedance calibration ? on-die termination (odt) ? pci interface ? pci specification revision 2.3 compatible
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 6 freescale semiconductor overview ? data bus widths: ? single 32-bit data pci interface that operates at up to 66 mhz ? pci 3.3-v compatible (not 5-v compatible) ? pci host bridge capabilities on both interfaces ? pci agent mode supported on pci interface ? support for pci-to-memory and memory-to-pci streaming ? memory prefetching of pci read accesses and support for delayed read transactions ? support for posting of processor-to-pci and pci-to-memory writes ? on-chip arbitration, supporting five masters on pci ? support for accesses to all pci address spaces ? parity support ? selectable hardware-enforced coherency ? address translation units for addres s mapping between host and peripheral ? dual address cycle supported when the device is the target ? internal configuration registers accessible from pci ? local bus controller (lbc) ? multiplexed 32-bit address and data operating at up to 133 mhz ? eight chip selects support eight external slaves ? up to eight-beat burst transfers ? 32-, 16-, and 8-bit port sizes are cont rolled by an on-chip memory controller ? three protocol engines availabl e on a per chip select basis: ? general-purpose chip select machine (gpcm) ? three user programmable machines (upms) ? dedicated single data rate sdram controller ? parity support ? default boot rom chip select with configurable bus width (8-, 16-, or 32-bit) ? programmable interrupt controller (pic) ? functional and programming compatibility with the mpc8260 interrupt controller ? support for 8 external and 35 internal discrete interrupt sources ? support for one external (optional) and seve n internal machine checkstop interrupt sources ? programmable highest priority request ? four groups of interrupts with programmable priority ? external and internal interrupts di rected to communication processor ? redirects interrupts to external inta pin when in core disable mode ? unique vector number for each interrupt source ? dual industry-standard i 2 c interfaces ? two-wire interface
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 freescale semiconductor 7 electrical characteristics ? multiple master support ? master or slave i 2 c mode support ? on-chip digital filtering rejects spikes on the bus ? system initialization data is optionally loaded from i 2 c-1 eprom by boot sequencer embedded hardware ? dma controller ? four independent virtual channels ? concurrent execution across multiple channels with programmable bandwidth control ? all channels accessible by local core and remote pci masters ? misaligned transfer capability ? data chaining and direct mode ? interrupt on completed segment and chain ? dma external handshake signals: dma_dreq [0:3]/dma_dack [0:3]/dma_done [0:3]. there is one set for each dma channel. the pins are multiplexed to the parallel io pins with other qe functions. ? duart ? two 4-wire interfaces (rxd, txd, rts, cts) ? programming model compatible with the original 16450 uart and the pc16550d ? system timers ? periodic interrupt timer ? real-time clock ? software watchdog timer ? eight general-purpose timers ? ieee std. 1149.1?-compliant, jtag boundary scan ? integrated pci bus and sdram clock generation 2 electrical characteristics this section provides the ac and dc electrical specifications and thermal characteristics for the mpc8358e. the device is currently targeted to these specifications. some of these specifications are independent of the i/o cell, but are included for a more complete reference. these are not purely i/o buffer design specifications.
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 8 freescale semiconductor electrical characteristics 2.1 overall dc electrical characteristics this section covers the ratings, conditions, and other characteristics. 2.1.1 absolute maximum ratings table 1 provides the absolute maximum ratings. table 1. absolute maximum ratings 1 characteristic symbol max value unit notes core supply voltage v dd ?0.3 to 1.32 v? pll supply voltage av dd ?0.3 to 1.32 v? ddr and ddr2 dram i/o voltage ddr ddr2 gv dd ?0.3 to 2.75 ?0.3 to 1.89 v? three-speed ethernet i/o, mii management voltage lv dd ?0.3 to 3.63 v ? pci, local bus, duart, system control and power management, i 2 c, spi, and jtag i/o voltage ov dd ?0.3 to 3.63 v ? input voltage ddr dram signals mv in ? 0.3 to (gv dd + 0.3) v 2, 5 ddr dram reference mv ref ? 0.3 to (gv dd + 0.3) v 2, 5 three-speed ethernet signals lv in ?0.3 to (lv dd + 0.3) v 4, 5 local bus, duart, clkin, system control and power management, i 2 c, spi, and jtag signals ov in ? 0.3 to (ov dd + 0.3) v 3, 5 pci ov in ? 0.3 to (ov dd + 0.3) v 6 storage temperature range t stg ? 55 to 150 c? notes: 1. functional and tested operating conditions are given in ta b l e 2 . absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. caution: m v in must not exceed gv dd by more than 0.3 v. this limit may be exceeded for a maximum of 100 ms during power-on reset and power-down sequences. 3. caution: ov in must not exceed ov dd by more than 0.3 v. this limit may be exceeded for a maximum of 100 ms during power-on reset and power-down sequences. 4. caution: lv in must not exceed lv dd by more than 0.3 v. this limit may be exceeded for a maximum of 100 ms during power-on reset and power-down sequences. 5. (m,l,o)v in and mv ref may overshoot/undershoot to a voltage and for a maximum duration as shown in figure 2 . 6. ov in on the pci interface may overshoot/undershoot according to the pci electrical specification for 3.3-v operation, as shown in figure 3 .
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 freescale semiconductor 9 electrical characteristics 2.1.2 power supply voltage specification table 2 provides the recommended operating conditions fo r the device. note that the values in table 2 are the recommended and tested operating conditions. prope r device operation outside of these conditions is not guaranteed. table 2. recommended operating conditions characteristic symbol recommended value unit notes core supply voltage v dd 1.2 v 60 mv v 1 pll supply voltage av dd 1.2 v 60 mv v 1 ddr and ddr2 dram i/o supply voltage ddr ddr2 gv dd 2.5 v 125 mv 1.8 v 90 mv v? three-speed ethernet i/o supply voltage lv dd 0 3.3 v 330 mv 2.5 v 125 mv v? three-speed ethernet i/o supply voltage lv dd 1 3.3 v 330 mv 2.5 v 125 mv v? three-speed ethernet i/o supply voltage lv dd 2 3.3 v 330 mv 2.5 v 125 mv v? pci, local bus, duart, system control and power management, i 2 c, spi, and jtag i/o voltage ov dd 3.3 v 330 mv v ? junction temperature t j 0 to 105 ? 40 to 105 c? notes: 1. gv dd , lv dd , ov dd , av dd , and v dd must track each other and must vary in the same direction?either in the positive or negative direction.
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 10 freescale semiconductor electrical characteristics figure 2 shows the undershoot and overshoot voltages at the interfaces of the device. figure 2. overshoot/undershoot voltage for gv dd /ov dd /lv dd figure 3 shows the undershoot and overshoot voltage of the pci interface of the device for the 3.3-v signals, respectively. figure 3. maximum ac waveforms on pci interface for 3.3-v signaling gnd gnd ? 0.3 v gnd ? 0.7 v not to exceed 10% g/l/ov dd + 20% g/l/ov dd g/l/ov dd + 5% of t interface 1 1. note that t interface refers to the clock period associated with the bus clock interface. v ih v il note: undervoltage waveform overvoltage waveform 11 ns (min) +7.1 v 7.1 v p-to-p (min) 4 ns (max) ?3.5 v 7.1 v p-to-p (min) 62.5 ns +3.6 v 0 v 4 ns (max)
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 freescale semiconductor 11 electrical characteristics 2.1.3 output driver characteristics table 3 provides information on the characteristics of the output driver strengths. the values are preliminary estimates. 2.2 power sequencing this section details the power sequenc ing considerations for the mpc8358e. 2.2.1 power-up sequencing mpc8358e does not require the core supply voltage (v dd and av dd ) and i/o supply voltages (gv dd , lv dd , and ov dd ) to be applied in any par ticular order. during the power ramp up, before the power supplies are stable and if the i/o voltages are supplie d before the core voltage, there may be a period of time that all input and output pins will actively be driven and cause contention and excessive current. in order to avoid actively driving the i/o pins and to eliminate excessive current draw, apply the core voltage (v dd ) before the i/o voltage (gv dd , lv dd , and ov dd ) and assert poreset before the power supplies fully ramp up. in the case where the core voltage is applied first, the core voltage supply must rise to 90% of its nominal value before the i/o supplies reach 0.7 v, see figure 4 . table 3. output drive capability driver type output impedance ( ) supply voltage local bus interface utilities signals 42 ov dd = 3.3 v pci signals 25 pci output clocks (including pci_sync_out) 42 ddr signal 20 36 (half-strength mode) 1 1 ddr output impedance values for half strength mode are verified by design and not tested. gv dd = 2.5 v ddr2 signal 18 36 (half-strength mode) 1 gv dd = 1.8 v 10/100/1000 ethernet signals 42 lv dd = 2.5/3.3 v duart, system control, i 2 c, spi, jtag 42 ov dd = 3.3 v gpio signals 42 ov dd = 3.3 v lv dd = 2.5/3.3 v
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 12 freescale semiconductor power characteristics figure 4. power sequencing example i/o voltage supplies (gv dd , lv dd , and ov dd ) do not have any ordering requi rements with respect to one another. 2.2.2 power-down sequencing the mpc8358e does not require the core supply voltage and i/o supply voltages to be powered down in any particular order. 3 power characteristics the estimated typical power dissipation values are shown in table 4 . table 4. mpc8358e pbga core power dissipation 1 core frequency (mhz) csb frequency (mhz) quicc engine frequency (mhz) typical maximum unit notes 266 266 266 2.2 2.3 w 2, 3, 4 400 266 266 2.4 2.5 w 2, 3, 4 400 266 400 2.5 2.6 w 2, 3, 4 notes: 1. the values do not include i/o supply power (ov dd , lv dd , gv dd ) or av dd . for i/o power values, see ta ble 5 . 2. typical power is based on a voltage of v dd = 1.2 v, a junction temperature of t j = 105 c, and a dhrystone benchmark application. 3. thermal solutions will likely need to design to a value higher than typical power on the end application, t a target, and i/o power. 4. maximum power is based on a voltage of v dd = 1.2 v, wc process, a junction t j = 105 c, and an artificial smoke test. i/o voltage (gv dd , lv dd , ov dd ) core voltage (v dd , av dd ) 90% 0.7 v time voltage
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 freescale semiconductor 13 clock input timing table 5 shows the estimated typical i/o power dissipation for the device. 4 clock input timing this section provides the clock input dc and ac electrical characteristics for the mpc8358e. note the rise/fall time on quicc engine block input pins should not exceed 5 ns. this should be enforced especially on clock signals. rise time refers to signal transitions from 10% to 90% of v dd ; fall time refers to transitions from 90% to 10% of v dd . table 5. estimated typical i/o power dissipation interface parameter gv dd (1.8 v) gv dd (2.5 v) ov dd (3.3 v) lv dd (3.3 v) lv dd (2.5 v) unit comments ddr i/o 65% utilization 2.5 v r s = 20 r t = 50 2 pairs of clocks 200 mhz, 1x32 bits 0.3 0.46 ? ? ? w ? 200 mhz, 1x64 bits 0.4 0.58 ? ? ? w ? 200 mhz, 2x32 bits 0.6 0.92 ? ? ? w ? 266 mhz, 1x32 bits 0.35 0.56 ? ? ? w ? 266 mhz, 1x64 bits 0.46 0.7 ? ? ? w ? 266 mhz, 2x32 bits 0.7 1.11 ? ? ? w ? local bus i/o load = 25 pf 3 pairs of clocks 133 mhz, 32 bits ? ? 0.22 ? ? w ? 83 mhz, 32 bits ? ? 0.14 ? ? w ? 66 mhz, 32 bits ? ? 0.12 ? ? w ? 50 mhz, 32 bits ? ? 0.09 ? ? w ? pci i/o load = 30 pf 33 mhz, 32 bits ? ? 0.05 ? ? w ? 66 mhz, 32 bits ? ? 0.07 ? ? w ? 10/100/1000 ethernet i/o load = 20 pf mii or rmii ? ? ? 0.01 ? w multiply by number of interfaces used. gmii or tbi ? ? ? 0.04 ? w rgmii or rtbi ????0.04w other i/o ? ? ? 0.1 ? ? w ?
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 14 freescale semiconductor clock input timing 4.1 dc electrical characteristics table 6 provides the clock input (clkin/pci_sync_i n) dc timing specifications for the device. 4.2 ac electrical characteristics the primary clock source for the device can be one of two inputs, clkin or pci_clk, depending on whether the device is configured in pci host or pci agent mode. table 7 provides the clock input (clkin/pci_clk) ac timing specifications for the device. table 6. clkin dc electrical characteristics parameter condition symbol min max unit input high voltage ? v ih 2.7 ov dd + 0.3 v input low voltage ? v il ?0.3 0.4 v clkin input current 0 v v in ov dd i in ?10 a pci_sync_in input current 0 v v in 0.5v or ov dd ? 0.5v v in ov dd i in ?10 a pci_sync_in input current 0.5 v v in ov dd ? 0.5 v i in ?100 a table 7. clkin ac timing specifications parameter/condition symbol min typical max unit notes clkin/pci_clk frequency f clkin ? ? 66.67 mhz 1 clkin/pci_clk cycle time t clkin 15 ? ? ns ? clkin/pci_clk rise and fall time t kh , t kl 0.6 1.0 2.3 ns 2 clkin/pci_clk duty cycle t khk /t clkin 40 ? 60 % 3 clkin/pci_clk jitter ? ? ? 150 ps 4, 5 notes: 1. caution: the system, core, usb, security, and 10/100/1000 ethernet must not exceed their respective maximum or minimum operating frequencies. 2. rise and fall times for clkin/pci_clk are measured at 0.4 v and 2.7 v. 3. timing is guaranteed by design and characterization. 4. this represents the total input jitter?short term and long term?and is guaranteed by design. 5. the clkin/pci_clk driver?s closed loop jitter bandwidth should be <500 khz at ?20 db. the bandwidth must be set low to allow cascade-connected pll-based devices to track clkin drivers with the specified jitter.
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 freescale semiconductor 15 reset initialization 4.3 gigabit reference clock input timing table 8 provides the gigabit reference clocks (gtx_clk125) ac timing specifications. 5 reset initialization this section describes the dc and ac electrical specifications for the reset initialization timing and electrical requirements of the mpc8358e. 5.1 reset dc electrical characteristics table 9 provides the dc electrical characteristics for the reset pins of the device. table 8. gtx_clk125 ac timing specifications at recommended operating conditions with lv dd = 2.5 0.125 mv/ 3.3 v 165 mv parameter/condition symbol min typical max unit notes gtx_clk125 frequency t g125 ? 125 ? mhz ? gtx_clk125 cycle time t g125 ?8?ns? gtx_clk rise and fall time lv dd = 2.5 v lv dd = 3.3 v t g125r /t g125f ?? 0.75 1.0 ns 1 gtx_clk125 duty cycle gmii & tbi 1000base-t for rgmii & rtbi t g125h /t g125 45 47 ? 55 53 %2 gtx_clk125 jitter ? ? ? 150 ps 2 notes: 1. rise and fall times for gtx_clk125 are measured from 0.5 and 2.0 v for lv dd = 2.5 v and from 0.6 and 2.7 v for lv dd =3.3v. 2. gtx_clk125 is used to generate the gtx clock for the ucc ethernet transmitter with 2% degradation. the gtx_clk125 duty cycle can be loosened from 47%/53% as long as the phy device can tolerate the duty cycle generated by gtx_clk. see section 8.2.2, ?mii ac timing specifications ,? section 8.2.3, ?rmii ac timing specifications ,? and section 8.2.5, ?rgmii and rtbi ac timing specifications? for the duty cycle for 10base-t and 100base-t reference clock. table 9. reset pins dc electrical characteristics characteristic symbol condition min max unit input high voltage v ih ?2.0ov dd + 0.3 v input low voltage v il ? ?0.3 0.8 v input current i in ??10 a output high voltage v oh i oh = ?8.0 ma 2.4 ? v output low voltage v ol i ol = 8.0 ma ? 0.5 v
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 16 freescale semiconductor reset initialization 5.2 reset ac electrical characteristics this section describes the ac electrical specifications for the reset initialization timing requirements of the device. table 10 provides the reset initialization ac timing specifications for the ddr sdram component(s). output low voltage v ol i ol = 3.2 ma ? 0.4 v notes: 1. this table applies for pins poreset , hreset , sreset , and quiesce . 2. hreset and sreset are open drain pins, thus v oh is not relevant for those pins. table 10. reset initialization timing specifications parameter/condition min max unit notes required assertion time of hreset or sreset (input) to activate reset flow 32 ? t pci_sync_in 1 required assertion time of poreset with stable clock applied to clkin when the device is in pci host mode 32 ? t clkin 2 required assertion time of poreset with stable clock applied to pci_sync_in when the device is in pci agent mode 32 ? t pci_sync_in 1 hreset /sreset assertion (output) 512 ? t pci_sync_in 1 hreset negation to sreset negation (output) 16 ? t pci_sync_in 1 input setup time for por config signals (cfg_reset_source[0:2] and cfg_clkin_div) with respect to negation of poreset when the device is in pci host mode 4?t clkin 2 input setup time for por config signals (cfg_reset_source[0:2] and cfg_clkin_div) with respect to negation of poreset when the device is in pci agent mode 4?t pci_sync_in 1 input hold time for por config signals with respect to negation of hreset 0? ns time for the device to turn off por config signals with respect to the assertion of hreset ?4 ns 3 time for the device to turn on por config signals with respect to the negation of hreset 1?t pci_sync_in 1, 3 notes: 1. t pci_sync_in is the clock period of the input clock applied to pci_sync_in. when the device is in pci host mode the primary clock is applied to the clkin input, and pci_sync_in period depends on the value of cfg_clkin_div. see the mpc8360e powerquicc ii pro integrated communications processor family reference manual for more details. 2. t clkin is the clock period of the input clock applied to clkin. it is only valid when the device is in pci host mode. see the mpc8360e powerquicc ii pro integrated communications processor family reference manual for more details. 3. por config signals consists of cfg_reset_source[0:2] and cfg_clkin_div. table 9. reset pins dc electrical characteristics (continued) characteristic symbol condition min max unit
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 freescale semiconductor 17 reset initialization table 11 provides the pll and dll lock times. 5.3 quicc engine block operating frequency limitations this section specify the limits of the ac electrical characteristics for the operation of the quicc engine block?s communication interfaces. note the settings listed below are required for correct hardware interface operation. each protocol by itself requires a minimal quicc engine block operating frequency setting for meeting the performance target. because the performance is a complex function of all the quicc engine block settings, the user should make use of the quicc engine block performance utility tool provided by freescale to validate their system. table 12 lists the maximal quicc engine block i/o fr equencies and the minimal quicc engine block core frequency for each interface. table 11. pll and dll lock times parameter/condition min max unit notes pll lock times ? 100 s? dll lock times 7680 122,880 csb_clk cycles 1, 2 notes: 1. dll lock times are a function of the ratio between the output clock and the coherency system bus clock (csb_clk). a 2:1 ratio results in the minimum and an 8:1 ratio results in the maximum. 2. the csb_clk is determined by the clkin and system pll ratio. see section 22, ?clocking,? for more information. table 12. quicc engine block operating frequency limitations interface interface operating frequency (mhz) max interface bit rate (mbps) min quicc engine operating frequency 1 (mhz) notes ethernet management: mdc/mdio 10 (max) 10 20 ? mii 25 (typ) 100 50 ? rmii 50 (typ) 100 50 ? gmii/rgmii/tbi/rtbi 125 (typ) 1000 250 ? spi (master/slave) 10 (max) 10 20 ? ucc through tdm 50 (max) 70 8 f2 mcc 25 (max) 16.67 16 f 2, 4 utopia l2 50 (max) 800 2 f2 pos-phy l2 50 (max) 800 2 f2 hdlc bus 10 (max) 10 20 ? hdlc/transparent 50 (max) 50 8/3 f2, 3
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 18 freescale semiconductor ddr and ddr2 sdram 6 ddr and ddr2 sdram this section describes the dc and ac electrical specifications for the ddr and ddr2 sdram interface of the mpc8358e. 6.1 ddr and ddr2 sdram dc electrical characteristics table 13 provides the recommended operating conditions for the ddr2 sdram component(s) of the device when gv dd (typ) = 1.8 v . uart/async hdlc 3.68 (max internal ref clock) 115 (kbps) 20 ? bisync 2 (max) 2 20 ? usb 48 (ref clock) 12 96 ? notes: 1. the quicc engine module needs to run at a frequency higher than or equal to what is listed in this table. 2. ?f? is the actual interface operating frequency. 3. the bit rate limit is independent of the data bus width (that is, the same for serial, nibble, or octal interfaces). 4. tdm in high-speed mode for serial data interface. table 13. ddr2 sdram dc electrical characteristics for gv dd (typ) = 1.8 v parameter/condition symbol min max unit notes i/o supply voltage gv dd 1.71 1.89 v 1 i/o reference voltage mv ref 0.49 gv dd 0.51 gv dd v2 i/o termination voltage v tt mv ref ? 0.04 mv ref + 0.04 v 3 input high voltage v ih mv ref + 0.125 gv dd + 0.3 v ? input low voltage v il ?0.3 mv ref ? 0.125 v ? output leakage current i oz ?10 a4 output high current (v out = 1.420 v) i oh ?13.4 ? ma ? output low current (v out = 0.280 v) i ol 13.4 ? ma ? mv ref input leakage current i vref ?10 a? table 12. quicc engine block operating frequency limitations (continued) interface interface operating frequency (mhz) max interface bit rate (mbps) min quicc engine operating frequency 1 (mhz) notes
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 freescale semiconductor 19 ddr and ddr2 sdram table 14 provides the ddr2 capacitance when gv dd (typ) = 1.8 v. table 15 provides the recommended operating conditions for the ddr sdram component(s) of the device when gv dd (typ) = 2.5 v. input current (0 v v in ov dd )i in ?10 a? notes: 1. gv dd is expected to be within 50 mv of the dram gv dd at all times. 2. mv ref is expected to equal 0.5 gv dd , and to track gv dd dc variations as measured at the receiver. peak-to-peak noise on mv ref cannot exceed 2% of the dc value. 3. v tt is not applied directly to the device. it is the supply to which far end signal termination is made and is expected to equal mv ref . this rail should track variations in the dc level of mv ref . 4. output leakage is measured with all outputs disabled, 0 v v out gv dd . table 14. ddr2 sdram capacitance for gv dd (typ)=1.8 v parameter/condition symbol min max unit notes input/output capacitance: dq, dqs, dqs c io 68pf1 delta input/output capacitance: dq, dqs, dqs c dio ?0.5pf1 note: 1. this parameter is sampled. gv dd = 1.8 v 0.090 v, f = 1 mhz, t a = 25c, v out = gv dd /2, v out (peak-to-peak) = 0.2 v. table 15. ddr sdram dc electrical characteristics for gv dd (typ) = 2.5 v parameter/condition symbol min max unit notes i/o supply voltage gv dd 2.375 2.625 v 1 i/o reference voltage mv ref 0.49 gv dd 0.51 gv dd v2 i/o termination voltage v tt mv ref ? 0.04 mv ref + 0.04 v 3 input high voltage v ih mv ref + 0.18 gv dd + 0.3 v ? input low voltage v il ?0.3 mv ref ? 0.18 v ? output leakage current i oz ?10 a4 output high current (v out = 1.95 v) i oh ?15.2 ? ma ? output low current (v out = 0.35 v) i ol 15.2 ? ma ? mv ref input leakage current i vref ?10 a? input current (0 v v in ov dd )i in ?10 a? notes: 1. gv dd is expected to be within 50 mv of the dram gv dd at all times. 2. mv ref is expected to be equal to 0.5 gv dd , and to track gv dd dc variations as measured at the receiver. peak-to-peak noise on mv ref may not exceed 2% of the dc value. 3. v tt is not applied directly to the device. it is the supply to which far end signal termination is made and is expected to be equal to mv ref . this rail should track variations in the dc level of mv ref . 4. output leakage is measured with all outputs disabled, 0 v v out gv dd . table 13. ddr2 sdram dc electrical characteristics for gv dd (typ) = 1.8 v (continued) parameter/condition symbol min max unit notes
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 20 freescale semiconductor ddr and ddr2 sdram table 16 provides the ddr capacitance when gv dd (typ) = 2.5 v. 6.2 ddr and ddr2 sdram ac electrical characteristics this section provides the ac electrical characteristics for the ddr and ddr2 sdram interface. 6.2.1 ddr and ddr2 sdram input ac timing specifications table 17 provides the input ac timing specifications for the ddr2 sdram interface when gv dd (typ) = 1.8 v. table 18 provides the input ac timing specifications for the ddr sdram interface when gv dd (typ) = 2.5 v. table 16. ddr sdram capacitance for gv dd (typ) = 2.5 v parameter/condition symbol min max unit notes input/output capacitance: dq, dqs c io 68pf1 delta input/output capacitance: dq, dqs c dio ?0.5pf1 note: 1. this parameter is sampled. gv dd = 2.5 v 0.125 v, f = 1 mhz, t a = 25 c, v out = gv dd /2, v out (peak-to-peak) = 0.2 v. table 17. ddr2 sdram input ac timing specifications for gv dd (typ) = 1.8 v at recommended operating conditions with gv dd of 1.8 v 5%. parameter symbol min max unit notes ac input low voltage v il ?mv ref ? 0.25 v ? ac input high voltage v ih mv ref + 0.25 ? v ? table 18. ddr sdram input ac timing specifications at recommended operating conditions with gv dd of 2.5 v 5%. parameter symbol min max unit notes ac input low voltage v il ?mv ref ? 0.31 v ? ac input high voltage v ih mv ref + 0.31 ? v ? note: 1. maximum possible skew between a data strobe (mdqs[n]) and any corresponding bit of data (mdq[8n + {0...7}] if 0 n 7) or ecc (mecc[{0...7}] if n = 8).
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 freescale semiconductor 21 ddr and ddr2 sdram figure 5 shows the input timing diagram for the ddr controller. figure 5. ddr input timing diagram 6.2.2 ddr and ddr2 sdram output ac timing specifications table 20 and table 21 provide the output ac timing specifications and measurement conditions for the ddr and ddr2 sdram interface. table 19. ddr and ddr2 sdram input ac timing specifications mode at recommended operating conditions with gv dd of (1.8 or 2.5 v) 5%. parameter symbol min max unit notes mdqs?mdq/mecc input skew per byte 266 mhz 200 mhz t diskew ?1125 ?1250 1125 1250 ps 1, 2 notes: 1. ac timing values are based on the ddr data rate, which is twice the ddr memory bus frequency. 2. maximum possible skew between a data strobe (mdqs[n]) and any corresponding bit of data (mdq[8n + {0...7}] if 0 n 7) or ecc (mecc[{0...7}] if n = 8). table 20. ddr and ddr2 sdram output ac timing specifications for source synchronous mode at recommended operating conditions with gv dd of (1.8 v or 2.5 v) 5%. parameter 8 symbol 1 min max unit notes mck[n] cycle time, (mck[n]/mck [n] crossing) t mck 610ns2 skew between any mck to addr/cmd 266 mhz 200 mhz t aoskew ?1.1 ?1.2 0.3 0.4 ns 3 mck [n] mck[n] t mck mdq[x] mdqs[n] t diskew d1 d0 t diskew
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 22 freescale semiconductor ddr and ddr2 sdram addr/cmd output setup with respect to mck 266 mhz 200 mhz t ddkhas 2.8 3.5 ?ns4 addr/cmd output hold with respect to mck 266 mhz?ddr1 266 mhz?ddr2 200 mhz t ddkhax 2.6 2.8 3.5 ?ns4 mcs (n) output setup with respect to mck 266 mhz 200 mhz t ddkhcs 2.8 3.5 ?ns4 mcs (n) output hold with respect to mck 266 mhz 200 mhz t ddkhcx 2.7 3.5 ?ns4 mck to mdqs t ddkhmh ?0.75 0.6 ns 5 mdq/mecc/mdm output setup with respect to mdqs 266 mhz 200 mhz t ddkhds , t ddklds 1.0 1.2 ?ns6 mdq/mecc/mdm output hold with respect to mdqs 266 mhz 200 mhz t ddkhdx , t ddkldx 1.0 1.2 ?ns6 mdqs preamble start t ddkhmp ?0.5 t mck ? 0.6 ?0.5 t mck + 0.6 ns 7 table 20. ddr and ddr2 sdram output ac timing specifications for source synchronous mode (continued) at recommended operating conditions with gv dd of (1.8 v or 2.5 v) 5%. parameter 8 symbol 1 min max unit notes
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 freescale semiconductor 23 ddr and ddr2 sdram figure 6 shows the ddr sdram output timing for address skew with respect to any mck. figure 6. timing diagram for t aoskew measurement mdqs epilogue end t ddkhme ?0.6 0.9 ns 7 notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. output hold time can be read as ddr timing (dd) from the rising or falling edge of the reference clock (kh or kl) until the output went invalid (ax or dx). for example, t ddkhas symbolizes ddr timing (dd) for the time t mck memory clock reference (k) goes from the high (h) state until outputs (a) are setup (s) or output valid time. also, t ddkldx symbolizes ddr timing (dd) for the time t mck memory clock reference (k) goes low (l) until data outputs (d) are invalid (x) or data output hold time. 2. all mck/mck referenced measurements are made from the crossing of the two signals 0.1 v. 3. in the source synchronous mode, mck/mck can be shifted in ? applied cycle increments through the clock control register. for the skew measurements referenced for t aoskew it is assumed that the clock adjustment is set to align the address/command valid with the rising edge of mck. 4. addr/cmd includes all ddr sdram output signals except mck/mck , mcs , and mdq/mecc/mdm/mdqs. for the addr/cmd setup and hold specifications, it is assumed that the clock control register is set to adjust the memory clocks by ? applied cycle. 5. note that t ddkhmh follows the symbol conventions described in note 1. for example, t ddkhmh describes the ddr timing (dd) from the rising edge of the mck(n) clock (kh) until the mdqs signal is valid (mh). t ddkhmh can be modified through control of the dqss override bits in the timing_cfg_2 register. in source synchronous mode, this will typically be set to the same delay as the clock adjust in the clk_cntl register. the timing parameters listed in the table assume that these two parameters have been set to the same adjustment value. see the mpc8360e powerquicc ii pro integrated communications processor family reference manual for a description and understanding of the timing modifications enabled by use of these bits. 6. determined by maximum possible skew between a data strobe (mdqs) and any corresponding bit of data (mdq), ecc (mecc), or data mask (mdm). the data strobe should be centered inside of the data eye at the pins of the device. 7. all outputs are referenced to the rising edge of mck(n) at the pins of the device. note that t ddkhmp follows the symbol conventions described in note 1. 8. ac timing values are based on the ddr data rate, which is twice the ddr memory bus frequency. table 20. ddr and ddr2 sdram output ac timing specifications for source synchronous mode (continued) at recommended operating conditions with gv dd of (1.8 v or 2.5 v) 5%. parameter 8 symbol 1 min max unit notes addr/cmd mck [n] mck[n] t mck cmd noop t aoskew(min) addr/cmd cmd noop t aoskew(max)
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 24 freescale semiconductor ddr and ddr2 sdram figure 7 provides the ac test load for the ddr bus. figure 7. ddr ac test load figure 8 shows the ddr sdram output timing diagram for source synchronous mode. figure 8. ddr sdram output timing diagram for source synchronous mode table 21. ddr and ddr2 sdram measurement conditions symbol ddr ddr2 unit notes v th mv ref 0.31 v mv ref 0.25 v v 1 v out 0.5 gv dd 0.5 gv dd v2 notes: 1. data input threshold measurement point. 2. data output measurement point. output z 0 = 50 gv dd /2 r l = 50
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 freescale semiconductor 25 duart 7duart this section describes the dc and ac electri cal specifications for the duart interface of the mpc8358e. 7.1 duart dc electrical characteristics table 22 provides the dc electrical characteristics for the duart interface of the device. 7.2 duart ac electrical specifications table 23 provides the ac timing parameters for the duart interface of the device. 8 ucc ethernet controller: three-speed ethernet, mii management this section provides the ac and dc electrical characteristics for three-speed, 10/100/1000, and mii management. table 22. duart dc electrical characteristics parameter symbol min max unit notes high-level input voltage v ih 2ov dd + 0.3 v ? low-level input voltage ov dd v il ?0.3 0.8 v ? high-level output voltage, i oh = ?100 av oh ov dd ? 0.4 ? v ? low-level output voltage, i ol = 100 av ol ?0.2v? input current (0 v v in ov dd )i in ?10 a1 note: 1. note that the symbol v in , in this case, represents the ov in symbol referenced in ta b l e 1 and ta b l e 2 . table 23. duart ac timing specifications parameter value unit notes minimum baud rate 256 baud ? maximum baud rate >1,000,000 baud 1 oversample rate 16 ? 2 notes: 1. actual attainable baud rate will be limited by the latency of interrupt processing. 2. the middle of a start bit is detected as the eighth sampled 0 after the 1-to-0 transition of the start bit. subsequent bit va lues are sampled each sixteenth sample.
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 26 freescale semiconductor ucc ethernet controller: three-speed ethernet, mii management 8.1 three-speed ethernet controller (10/100/1000 mbps)? gmii/mii/rmii/tbi/rgmii/rtbi electrical characteristics the electrical characteristics specified here apply to all gmii (gigabit media independent interface), mii (media independent interface), rmii (reduced media independent interface), tbi (ten-bit interface), rgmii (reduced gigabit media independent interface), and rtbi (reduced ten-bit interface) signals except mdio (management data input/output) and mdc (man agement data clock). the mii, rmii, gmii, and tbi interfaces are only defined for 3.3 v, while the rgmii and rtbi interfaces are only defined for 2.5 v. the rgmii and rtbi interfaces follow the hewlett-packard reduced pin-count interface for gigabit ethernet physical layer device sp ecification version 1.2a (9/22/2000). the electrical characteristics for the mdio and mdc are specified in section 8.3, ?ethernet management interface electrical characteristics.? 8.1.1 10/100/1000 ethernet dc electrical characteristics the electrical characteristics specified here apply to media independent interface (mii), reduced gigabit media independent interface (rgmii), reduced ten-bit interface (rtbi), reduced media independent interface (rmii) signals, management data input/ output (mdio) and manageme nt data clock (mdc). the mii and rmii interfaces are defined for 3.3 v, while the rgmii and rtbi interfaces can be operated at 2.5 v. the rgmii and rtbi interfaces follow the reduced gigabit media-independent interface (rgmii) specification version 1.3. the rmii interface follows the rmii consortium rmii specification version 1.2. table 24. rgmii/rtbi, gmii, tbi, mii, and rmii dc electrical characteristics (when operating at 3.3 v) parameter symbol conditions min max unit notes supply voltage 3.3 v lv dd ? 2.97 3.63 v 1 output high voltage v oh i oh = ?4.0 ma lv dd = min 2.40 lv dd + 0.3 v ? output low voltage v ol i ol = 4.0 ma lv dd = min gnd 0.50 v ? input high voltage v ih ??2.0lv dd + 0.3 v ? input low voltage v il ? ? ?0.3 0.90 v ? input current i in 0 v v in lv dd ?10 a? note: 1. gmii/mii pins that are not needed for rgmii, rmii, or rtbi operation are powered by the ov dd supply.
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 freescale semiconductor 27 ucc ethernet controller: three-speed ethernet, mii management 8.2 gmii, mii, rmii, tbi, rgmii, and rtbi ac timing specifications the ac timing specifications for gmii, mii, tbi, rgmii, and rtbi are presented in this section. 8.2.1 gmii timing specifications this sections describe the gmii transmit and receive ac timing specifications. 8.2.1.1 gmii transmit ac timing specifications table 26 provides the gmii transmit ac timing specifications. table 25. rgmii/rtbi dc electrical characteristics (when operating at 2.5 v) parameters symbol conditions min max unit supply voltage 2.5 v lv dd ? 2.37 2.63 v output high voltage v oh i oh = ?1.0 ma lv dd = min 2.00 lv dd + 0.3 v output low voltage v ol i ol = 1.0 ma lv dd = min gnd ? 0.3 0.40 v input high voltage v ih ?lv dd = min 1.7 lv dd + 0.3 v input low voltage v il ?lv dd = min ?0.3 0.70 v input current i in 0 v v in lv dd ?10 a table 26. gmii transmit ac timing specifications at recommended operating conditions with lv dd /ov dd of 3.3 v 10%. parameter/condition symbol 1 min typ max unit notes gtx_clk clock period t gtx ?8.0?ns? gtx_clk duty cycle t gtxh/tgtx 40 ? 60 % ? gtx_clk to gmii data txd[7:0], tx_er, tx_en delay t gtkhdx t gtkhdv 0.5 ? ?? 5.0 ns ? gtx_clk clock rise time, (20% to 80%) t gtxr ??1.0ns? gtx_clk clock fall time, (80% to 20%) t gtxf ??1.0ns? gtx_clk125 clock period t g125 ?8.0?ns2 gtx_clk125 reference clock duty cycle measured at lv dd/2 t g125h /t g125 45 ? 55 % 2 notes: 1. the symbols used for timing specifications follow the pattern t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t gtkhdv symbolizes gmii transmit timing (gt) with respect to the t gtx clock reference (k) going to the high state (h) relative to the time date input signals (d) reaching the valid state (v) to state or setup time. also, t gtkhdx symbolizes gmii transmit timing (gt) with respect to the t gtx clock reference (k) going to the high state (h) relative to the time date input signals (d) going invalid (x) or hold time. note that , in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for example, the subscript of t gtx represents the gmii(g) transmit (tx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. this symbol is used to represent the external gtx_clk125 signal and does not follow the original symbol naming convention.
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 28 freescale semiconductor ucc ethernet controller: three-speed ethernet, mii management figure 9 shows the gmii transmit ac timing diagram. figure 9. gmii transmit ac timing diagram 8.2.1.2 gmii receive ac timing specifications table 27 provides the gmii receive ac timing specifications. table 27. gmii receive ac timing specifications at recommended operating conditions with lv dd /ov dd of 3.3 v 10%. parameter/condition symbol 1 min typ max unit notes rx_clk clock period t grx ?8.0?ns? rx_clk duty cycle t grxh /t grx 40 ? 60 % ? rxd[7:0], rx_dv, rx_er setup time to rx_clk t grdvkh 2.0 ? ? ns ? rxd[7:0], rx_dv, rx_er hold time to rx_clk t grdxkh 0.3 ? ? ns ? rx_clk clock rise time, (20% to 80%) t grxr ??1.0ns? rx_clk clock fall time, (80% to 20%) t grxf ??1.0ns? notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t grdvkh symbolizes gmii receive timing (gr) with respect to the time data input signals (d) reaching the valid state (v) relative to the t rx clock reference (k) going to the high state (h) or setup time. also, t grdxkl symbolizes gmii receive timing (gr) with respect to the time data input signals (d) went invalid (x) relative to the t grx clock reference (k) going to the low (l) state or hold time. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for example, the subscript of t grx represents the gmii (g) receive (rx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). gtx_clk txd[7:0] t gtkhdx t gtx t gtxh t gtxr t gtxf tx_en tx_er
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 freescale semiconductor 29 ucc ethernet controller: three-speed ethernet, mii management figure 10 shows the gmii receive ac timing diagram. figure 10. gmii receive ac timing diagram 8.2.2 mii ac timing specifications this section describes the mii transmit and receive ac timing specifications. 8.2.2.1 mii transmit ac timing specifications table 28 provides the mii transmit ac timing specifications. table 28. mii transmit ac timing specifications at recommended operating conditions with lv dd /ov dd of 3.3 v 10%. parameter/condition symbol 1 min typ max unit tx_clk clock period 10 mbps t mtx ?400?ns tx_clk clock period 100 mbps t mtx ?40?ns tx_clk duty cycle t mtxh /t mtx 35 ? 65 % tx_clk to mii data txd[3:0], tx_er, tx_en delay t mtkhdx t mtkhdv 1 ? 5? 15 ns tx_clk data clock rise time, (20% to 80%) t mtxr 1.0 ? 4.0 ns tx_clk data clock fall time, (80% to 20%) t mtxf 1.0 ? 4.0 ns note: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mtkhdx symbolizes mii transmit timing (mt) for the time t mtx clock reference (k) going high (h) until data outputs (d) are invalid (x). note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. for example, the subscript of t mtx represents the mii(m) transmit (tx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). rx_clk rxd[7:0] t grdxkh t grx t grxh t grxr t grxf t grdvkh rx_dv rx_er
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 30 freescale semiconductor ucc ethernet controller: three-speed ethernet, mii management figure 11 shows the mii transmit ac timing diagram. figure 11. mii transmit ac timing diagram 8.2.2.2 mii receive ac timing specifications table 29 provides the mii receive ac timing specifications. figure 12 provides the ac test load. figure 12. ac test load table 29. mii receive ac timing specifications at recommended operating conditions with lv dd /ov dd of 3.3 v 10%. parameter/condition symbol 1 min typ max unit rx_clk clock period 10 mbps t mrx ?400?ns rx_clk clock period 100 mbps t mrx ?40?ns rx_clk duty cycle t mrxh /t mrx 35 ? 65 % rxd[3:0], rx_dv, rx_er setup time to rx_clk t mrdvkh 10.0 ? ? ns rxd[3:0], rx_dv, rx_er hold time to rx_clk t mrdxkh 10.0 ? ? ns rx_clk clock rise time, (20% to 80%) t mrxr 1.0 ? 4.0 ns rx_clk clock fall time, (80% to 20%) t mrxf 1.0 ? 4.0 ns note: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mrdvkh symbolizes mii receive timing (mr) with respect to the time data input signals (d) reach the valid state (v) relative to the t mrx clock reference (k) going to the high (h) state or setup time. also, t mrdxkl symbolizes mii receive timing (gr) with respect to the time data input signals (d) went invalid (x) relative to the t mrx clock reference (k) going to the low (l) state or hold time. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for example, the subscript of t mrx represents the mii (m) receive (rx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). tx_clk txd[3:0] t mtkhdx t mtx t mtxh t mtxr t mtxf tx_en tx_er output z 0 = 50 lv dd /2 r l = 50
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 freescale semiconductor 31 ucc ethernet controller: three-speed ethernet, mii management figure 13 shows the mii receive ac timing diagram. figure 13. mii receive ac timing diagram 8.2.3 rmii ac timing specifications this section describes the rmii transmit and receive ac timing specifications. 8.2.3.1 rmii transmit ac timing specifications table 30 provides the rmii transmit ac timing specifications. table 30. rmii transmit ac timing specifications at recommended operating conditions with lv dd /ov dd of 3.3 v 10%. parameter/condition symbol 1 min typ max unit ref_clk clock t rmx ?20?ns ref_clk duty cycle t rmxh /t rmx 35 ? 65 % ref_clk to rmii data txd[1:0], tx_en delay t rmtkhdx t rmtkhdv 2 ? ?? 10 ns ref_clk data clock rise time t rmxr 1.0 ? 4.0 ns ref_clk data clock fall time t rmxf 1.0 ? 4.0 ns note: 1. the symbols used for timing specifications follow the pattern of t (first three letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t rmtkhdx symbolizes rmii transmit timing (rmt) for the time t rmx clock reference (k) going high (h) until data outputs (d) are invalid (x). note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. for example, the subscript of t rmx represents the rmii(rm) reference (x) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). rx_clk rxd[3:0] t mrdxkh t mrx t mrxh t mrxr t mrxf rx_dv rx_er t mrdvkh valid data
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 32 freescale semiconductor ucc ethernet controller: three-speed ethernet, mii management figure 14 shows the rmii transmit ac timing diagram. figure 14. rmii transmit ac timing diagram 8.2.3.2 rmii receive ac timing specifications table 31 provides the rmii receive ac timing specifications. figure 15 provides the ac test load. figure 15. ac test load table 31. rmii receive ac timing specifications at recommended operating conditions with lv dd /ov dd of 3.3 v 10%. parameter/condition symbol 1 min typ max unit ref_clk clock period t rmx ?20?ns ref_clk duty cycle t rmxh /t rmx 35 ? 65 % rxd[1:0], crs_dv, rx_er setup time to ref_clk t rmrdvkh 4.0 ? ? ns rxd[1:0], crs_dv, rx_er hold time to ref_clk t rmrdxkh 2.0 ? ? ns ref_clk clock rise time t rmxr 1.0 ? 4.0 ns ref_clk clock fall time t rmxf 1.0 ? 4.0 ns note: 1. the symbols used for timing specifications follow the pattern of t (first three letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t rmrdvkh symbolizes rmii receive timing (rmr) with respect to the time data input signals (d) reach the valid state (v) relative to the t rmx clock reference (k) going to the high (h) state or setup time. also, t rmrdxkl symbolizes rmii receive timing (rmr) with respect to the time data input signals (d) went invalid (x) relative to the t rmx clock reference (k) going to the low (l) state or hold time. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particul ar functional. for example, the subscript of t rmx represents the rmii (rm) reference (x) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). ref_clk txd[1:0] t rmtkhdx t rmx t rmxh t rmxr t rmxf tx_en output z 0 = 50 lv dd /2 r l = 50
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 freescale semiconductor 33 ucc ethernet controller: three-speed ethernet, mii management figure 16 shows the rmii receive ac timing diagram. figure 16. rmii receive ac timing diagram 8.2.4 tbi ac timing specifications this section describes the tbi trans mit and receive ac timing specifications. 8.2.4.1 tbi transmit ac timing specifications table 32 provides the tbi transmit ac timing specifications. table 32. tbi transmit ac timing specifications at recommended operating conditions with lv dd /ov dd of 3.3 v 10%. parameter/condition symbol 1 min typ max unit notes gtx_clk clock period t ttx ?8.0?ns? gtx_clk duty cycle t ttxh /t ttx 40 ? 60 % ? gtx_clk to tbi data tcg[9:0] delay t ttkhdx t ttkhdv 0.9 ? ?? 5.0 ns gtx_clk clock rise time, (20% to 80%) t ttxr ??1.0ns? gtx_clk clock fall time, (80% to 20%) t ttxf ??1.0ns? gtx_clk125 reference clock period t g125 ?8.0?ns2 gtx_clk125 reference clock duty cycle t g125h /t g125 45 ? 55 ns ? notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state )(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t ttkhdv symbolizes the tbi transmit timing (tt) with respect to the time from t ttx (k) going high (h) until the referenced data signals (d) reach the valid state (v) or setup time. also, t ttkhdx symbolizes the tbi transmit timing (tt) with respect to the time from t ttx (k) going high (h) until the referenced data signals (d) reach the invalid state (x) or hold time. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for example, the subscript of t ttx represents the tbi (t) transmit (tx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. this symbol is used to represent the external gtx_clk125 and does not follow the original symbol naming convention. ref_clk rxd[1:0] t rmrdxkh t rmx t rmxh t rmxr t rmxf crs_dv rx_er t rmrdvkh valid data
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 34 freescale semiconductor ucc ethernet controller: three-speed ethernet, mii management figure 17 shows the tbi transmit ac timing diagram. figure 17. tbi transmit ac timing diagram 8.2.4.2 tbi receive ac timing specifications table 33 provides the tbi receive ac timing specifications. table 33. tbi receive ac timing specifications at recommended operating conditions with lv dd /ov dd of 3.3 v 10%. parameter/condition symbol 1 min typ max unit notes pma_rx_clk clock period t trx ? 16.0 ? ns ? pma_rx_clk skew t sktrx 7.5 ? 8.5 ns ? rx_clk duty cycle t trxh /t trx 40 ? 60 % ? rcg[9:0] setup time to rising pma_rx_clk t trdvkh 2.5 ? ? ns 2 rcg[9:0] hold time to rising pma_rx_clk t trdxkh 1.0 ? ? ns 2 rx_clk clock rise time, v il (min) to v ih (max) t trxr 0.7 ? 2.4 ns ? rx_clk clock fall time, v ih (max) to v il (min) t trxf 0.7 ? 2.4 ns ? notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t trdvkh symbolizes tbi receive timing (tr) with respect to the time data input signals (d) reach the valid state (v) relative to the t trx clock reference (k) going to the high (h) state or setup time. also, t trdxkh symbolizes tbi receive timing (tr) with respect to the time data input signals (d) went invalid (x) relative to the t trx clock reference (k) going to the high (h) state. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for example, the subscript of t trx represents the tbi (t) receive (rx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). for symbols representing skews, the subscript is skew (sk) followed by the clock that is being skewed (trx). 2. setup and hold time of even numbered rcg are measured from riding edge of pma_rx_clk1. setup and hold time of odd numbered rcg are measured from riding edge of pma_rx_clk0. gtx_clk txd[7:0] t ttx t ttxh t ttxr t ttxf t ttkhdx tx_en tx_er
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 freescale semiconductor 35 ucc ethernet controller: three-speed ethernet, mii management figure 18 shows the tbi receive ac timing diagram. figure 18. tbi receive ac timing diagram 8.2.5 rgmii and rtbi ac timing specifications table 34 presents the rgmii and rtbi ac timing specifications. table 34. rgmii and rtbi ac timing specifications at recommended operating conditions with lv dd of 2.5 v 5%. parameter/condition symbol 1 min typ max unit notes data to clock output skew (at transmitter) t skrgtkhdx t skrgtkhdv ?0.5 ? ?? 0.5 ns data to clock input skew (at receiver) t skrgdxkh t skrgdvkh 1.1 ? ?? 2.6 ns 2 clock cycle duration t rgt 7.2 8.0 8.8 ns 3 duty cycle for 1000base-t t rgth /t rgt 45 50 55 % 4, 5 duty cycle for 10base-t and 100base-tx t rgth /t rgt 40 50 60 % 3, 5 rise time (20?80%) t rgtr ? ? 0.75 ns ? fall time (20?80%) t rgtf ? ? 0.75 ns ? gtx_clk125 reference clock period t g125 ?8.0?ns6 pma_rx_clk1 rcg[9:0] t trx t trxh t trxr t trxf t trdvkh pma_rx_clk0 t trdxkh t trdvkh t trdxkh t sktrx t trxh even rcg odd rcg
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 36 freescale semiconductor ucc ethernet controller: three-speed ethernet, mii management figure 19 shows the rgmii and rtbi ac timing and multiplexing diagrams. figure 19. rgmii and rtbi ac timing and multiplexing diagrams gtx_clk125 reference clock duty cycle t g125h /t g125 47 ? 53 % ? notes: 1. note that, in general, the clock reference symbol representation for this section is based on the symbols rgt to represent rgmii and rtbi timing. for example, the subscript of t rgt represents the tbi (t) receive (rx) clock. note also that the notation for rise (r) and fall (f) times follows the clock symbol that is being represented. for symbols representing skews, the subscript is skew (sk) followed by the clock that is being skewed (rgt). 2. this implies that pc board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns will be added to the associated clock signal. 3. for 10 and 100 mbps, t rgt scales to 400 ns 40 ns and 40 ns 4 ns, respectively. 4. duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long as the minimum duty cycle is not violated and stretching occurs for no more than three t rgt of the lowest speed transitioned between. 5. duty cycle reference is lv dd /2. 6. this symbol is used to represent the external gtx_clk125 and does not follow the original symbol naming convention. 7. in rev. 2.1 silicon, due to errata, t skrgtkhdx minimum is ?0.65 ns for ucc2 option 1 and ?0.9 for ucc2 option 2, and t skrgtkhdv maximum is 0.75 ns for ucc1 and ucc2 option 1 and 0.85 for ucc2 option 2. ucc1 does meet t skrgtkhdx minimum for rev. 2.1 silicon. table 34. rgmii and rtbi ac timing specifications (continued) at recommended operating conditions with lv dd of 2.5 v 5%. parameter/condition symbol 1 min typ max unit notes gtx_clk t rgt t rgth t skrgtkhdx tx_ctl txd[8:5] txd[7:4] txd[9] txerr txd[4] txen txd[3:0] (at transmitter) txd[8:5][3:0] txd[7:4][3:0] tx_clk (at phy) rx_ctl rxd[8:5] rxd[7:4] rxd[9] rxerr rxd[4] rxdv rxd[3:0] rxd[8:5][3:0] rxd[7:4][3:0] rx_clk (at phy) t skrgtkhdx t skrgtkhdx t skrgtkhdx
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 freescale semiconductor 37 ucc ethernet controller: three-speed ethernet, mii management 8.3 ethernet management interface electrical characteristics the electrical characteristics specified here apply to mii management interface signals mdio (management data input/output) and mdc (management data clock). the electrical characteristics for gmii, rgmii, tbi, and rtbi are specified in section 8.1, ?three-speed ethernet controller (10/100/1000 mbps)? gmii/mii/rmii/tbi/rgmii/rtbi electrical characteristics.? 8.3.1 mii management dc electrical characteristics the mdc and mdio are defined to operate at a supply voltage of 3.3 v. the dc electrical characteristics for mdio and mdc are provided in table 35 . 8.3.2 mii management ac electrical specifications table 36 provides the mii management ac timing specifications. table 35. mii management dc electrical characteristics when powered at 3.3 v parameter symbol conditions min max unit supply voltage (3.3 v) ov dd ? 2.97 3.63 v output high voltage v oh i oh = ?1.0 ma ov dd = min 2.10 ov dd + 0.3 v output low voltage v ol i ol = 1.0 ma ov dd = min gnd 0.50 v input high voltage v ih ?2.00?v input low voltage v il ??0.80v input current i in 0 v v in ov dd ?10 a table 36. mii management ac timing specifications at recommended operating conditions with lv dd is 3.3 v 10%. parameter/condition symbol 1 min typ max unit notes mdc frequency f mdc ?2.5?mhz2 mdc period t mdc ?400?ns? mdc clock pulse width high t mdch 32 ? ? ns ? mdc to mdio delay t mdtkhdx t mdtkhdv 10 ? ?? 110 ns 3 mdio to mdc setup time t mdrdvkh 10 ? ? ns ? mdio to mdc hold time t mdrdxkh 0??ns? mdc rise time t mdcr ? ? 10 ns ?
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 38 freescale semiconductor ucc ethernet controller: three-speed ethernet, mii management figure 20 shows the mii management ac timing diagram. figure 20. mii management interface timing diagram 8.3.3 ieee 1588 timer ac specifications table 37 provides the ieee 1588 timer ac specifications. mdc fall time t mdhf ? ? 10 ns ? notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mdkhdx symbolizes management data timing (md) for the time t mdc from clock reference (k) high (h) until data outputs (d) are invalid (x) or data hold time. also, t mdrdvkh symbolizes management data timing (md) with respect to the time data input signals (d) reach the valid state (v) relative to the t mdc clock reference (k) going to the high (h) state or setup time. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. this parameter is dependent on the csb_clk speed (that is, for a csb_clk of 267 mhz, the maximum frequency is 8.3 mhz and the minimum frequency is 1.2 mhz; for a csb_clk of 375 mhz, the maximum frequency is 11.7 mhz and the minimum frequency is 1.7 mhz). 3. this parameter is dependent on the ce_clk speed (that is, for a ce_clk of 200 mhz, the delay is 90 ns and for a ce_clk of 300 mhz, the delay is 63 ns). table 37. ieee 1588 timer ac specifications parameter symbol min max unit notes timer clock frequency t tmrck 070mhz1 input setup to timer clock t tmrcks ???2, 3 input hold from timer clock t tmrckh ???2, 3 output clock to output valid t gclknv 06ns? table 36. mii management ac timing specifications (continued) at recommended operating conditions with lv dd is 3.3 v 10%. parameter/condition symbol 1 min typ max unit notes mdc t mdrdxkh t mdc t mdch t mdcr t mdhf t mdtkhdx mdio mdio (input) (output) t mdrdvkh
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 freescale semiconductor 39 local bus 9 local bus this section describes the dc and ac electrical specifications for the local bus interface of the mpc8358e. 9.1 local bus dc electrical characteristics table 38 provides the dc electrical characteristics for the local bus interface. 9.2 local bus ac electrical specifications table 39 describes the general timing parameters of the local bus interface of the device. timer alarm to output valid t tmral ??? 2 notes: 1. the timer can operate on rtc_clock or tmr_clock. these clocks get muxed and any one of them can be selected. the minimum and maximum requirement for both rtc_clock and tmr_clock are the same. 2. these are asynchronous signals. 3. inputs need to be stable at least one tmr clock. table 38. local bus dc electrical characteristics parameter symbol min max unit high-level input voltage v ih 2ov dd + 0.3 v low-level input voltage v il ?0.3 0.8 v high-level output voltage, i oh = ?100 av oh ov dd ? 0.4 ? v low-level output voltage, i ol = 100 av ol ?0.2v input current i in ?10 a table 39. local bus general timing parameters?dll enabled parameter symbol 1 min max unit notes local bus cycle time t lbk 7.5 ? ns 2 input setup to local bus clock (except lupwait) t lbivkh1 1.7 ? ns 3, 4 lupwait input setup to local bus clock t lbivkh2 1.9 ? ns 3, 4 input hold from local bus clock (except lupwait) t lbixkh1 1.0 ? ns 3, 4 lupwait input hold from local bus clock t lbixkh2 1.0 ? ns 3, 4 lale output fall to lad output transition (latch hold time) t lbotot1 1.5 ? ns 5 lale output fall to lad output transition (latch hold time) t lbotot2 3.0 ? ns 6 lale output fall to lad output transition (latch hold time) t lbotot3 2.5 ? ns 7 table 37. ieee 1 588 timer ac specifications (continued) parameter symbol min max unit notes
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 40 freescale semiconductor local bus table 40 describes the general timing parameters of the local bus interface of the device. local bus clock to lale rise t lbkhlr ?4.5ns ? local bus clock to output valid (except lad/ldp and lale) t lbkhov1 ?4.5ns ? local bus clock to data valid for lad/ldp t lbkhov2 ?4.5ns 3 local bus clock to address valid for lad t lbkhov3 ?4.5ns 3 output hold from local bus clock (except lad/ldp and lale) t lbkhox1 1.0 ? ns 3 output hold from local bus clock for lad/ldp t lbkhox2 1.0 ? ns 3 local bus clock to output high impedance for lad/ldp t lbkhoz ?3.8ns ? notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t lbixkh1 symbolizes local bus timing (lb) for the input (i) to go invalid (x) with respect to the time the t lbk clock reference (k) goes high (h), in this case for clock one (1). also, t lbkhox symbolizes local bus timing (lb) for the t lbk clock reference (k) to go high (h), with respect to the output (o) going invalid (x) or output hold time. 2. all timings are in reference to rising edge of lsync_in. 3. all signals are measured from ov dd /2 of the rising edge of lsync_in to 0.4 ov dd of the signal in question for 3.3-v signaling levels. 4. input timings are measured at the pin. 5. t lbotot1 should be used when rcwh[lale] is not set and when the load on lale output pin is at least 10 pf less than the load on lad output pins. 6. t lbotot2 should be used when rcwh[lale] is set and when the load on lale output pin is at least 10 pf less than the load on lad output pins. 7. t lbotot3 should be used when rcwh[lale] is set and when the load on lale output pin equals to the load on lad output pins. 8. for purposes of active/float timing measurements, the hi-z or off-state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. table 40. local bus general timing parameters?dll bypass mode parameter symbol 1 min max unit notes local bus cycle time t lbk 15 ? ns 2 input setup to local bus clock t lbivkh 7?ns3, 4 input hold from local bus clock t lbixkh 1.0 ? ns 3, 4 lale output fall to lad output transition (latch hold time) t lbotot1 1.5 ? ns 5 lale output fall to lad output transition (latch hold time) t lbotot2 3?ns6 lale output fall to lad output transition (latch hold time) t lbotot3 2.5 ? ns 7 local bus clock to output valid t lbkhov ?3ns3 table 39. local bus general timing parameters?dll enabled (continued) parameter symbol 1 min max unit notes
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 freescale semiconductor 41 local bus figure 21 provides the ac test load for the local bus. figure 21. local bus c test load local bus clock to output high impedance for lad/ldp t lbkhoz ?4ns? notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t lbixkh1 symbolizes local bus timing (lb) for the input (i) to go invalid (x) with respect to the time the t lbk clock reference (k) goes high (h), in this case for clock one (1). also, t lbkhox symbolizes local bus timing (lb) for the t lbk clock reference (k) to go high (h), with respect to the output (o) going invalid (x) or output hold time. 2. all timings are in reference to falling edge of lclk0 (for all outputs and for lgta and lupwait inputs) or rising edge of lclk0 (for all other inputs). 3. all signals are measured from ov dd /2 of the rising/falling edge of lclk0 to 0.4 ov dd of the signal in question for 3.3-v signaling levels. 4. input timings are measured at the pin. 5. t lbotot1 should be used when rcwh[lale] is not set and when the load on lale output pin is at least 10 pf less than the load on lad output pins. 6. t lbotot2 should be used when rcwh[lale] is set and when the load on lale output pin is at least 10 pf less than the load on lad output pins. 7. t lbotot3 should be used when rcwh[lale] is set and when the load on lale output pin equals to the load on lad output pins. 8. for purposes of active/float timing measurements, the hi-z or off-state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 9. dll bypass mode is not recommended for use at frequencies above 66 mhz. table 40. local bus general timing parameters?dll bypass mode (continued) parameter symbol 1 min max unit notes output z 0 = 50 ov dd /2 r l = 50
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 42 freescale semiconductor local bus figure 22 through figure 27 show the local bus signals. figure 22. local bus signals, nonspecial signals only (dll enabled) figure 23. local bus signals, nonspecial signals only (dll bypass mode) output signals: la[27:31]/lbctl/lbcke/loe / lsda10/lsdwe/lsdras / lsdcas /lsddqm[0:3] t lbkhov t lbkhov t lbkhov lsync_in input signals: lad[0:31]/ldp[0:3] output (data) signals: lad[0:31]/ldp[0:3] output (address) signal: lad[0:31] lale t lbixkh t lbivkh t lbixkh t lbkhox t lbkhox t lbkhoz t lbkhlr t lbotot t lbkhoz t lbkhox output signals: la[27:31]/lbctl/lbcke/loe / lsda10/lsdwe/lsdras / lsdcas /lsddqm[0:3] t lbkhov t lbkhov lclk[n] input signals: lad[0:31]/ldp[0:3] output signals: lad[0:31]/ldp[0:3] t lbixkh t lbivkh t lbkhoz t lbotot lale input signal: lgta t lbixkh t lbivkh t lbixkh
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 freescale semiconductor 43 local bus figure 24. local bus signals, gpcm/upm signals for lcrr[clkdiv] = 2 (dll enabled) figure 25. local bus signals, gpcm/upm signals for lcrr[clkdiv] = 2 (dll bypass mode) lsync_in upm mode input signal: lupwait t lbixkh2 t lbivkh2 t lbivkh1 t lbixkh1 t lbkhoz1 t1 t3 input signals: lad[0:31]/ldp[0:3] upm mode output signals: lcs [0:3]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:3]/lwe t lbkhov1 t lbkhov1 t lbkhoz1 lclk upm mode input signal: lupwait t lbixkh t lbivkh t lbivkh t lbixkh t lbkhoz t1 t3 input signals: lad[0:31]/ldp[0:3] upm mode output signals: lcs [0:3]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:3]/lwe t lbkhov t lbkhov t lbkhoz (dll bypass mode)
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 44 freescale semiconductor local bus figure 26. local bus signals, gpcm/upm signals for lcrr[clkdiv] = 4 (dll bypass mode) lclk upm mode input signal: lupwait t lbixkh t lbivkh t lbivkh t lbixkh t lbkhoz t1 t3 upm mode output signals: lcs [0:3]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:3]/lwe t lbkhov t lbkhov t lbkhoz t2 t4 input signals: lad[0:31]/ldp[0:3] (dll bypass mode)
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 freescale semiconductor 45 jtag figure 27. local bus signals, gpcm/upm signals for lcrr[clkdiv] = 4 (dll enabled) 10 jtag this section describes the dc and ac electrical sp ecifications for the ieee 1149.1 (jtag) interface of the mpc8358e. 10.1 jtag dc electrical characteristics table 41 provides the dc electrical characteristics for th e ieee 1149.1 (jtag) interface of the device. table 41. jtag interface dc electrical characteristics characteristic symbol condition min max unit output high voltage v oh i oh = ?6.0 ma 2.4 ? v output low voltage v ol i ol = 6.0 ma ? 0.5 v output low voltage v ol i ol = 3.2 ma ? 0.4 v input high voltage v ih ?2.5ov dd + 0.3 v input low voltage v il ? ?0.3 0.8 v input current i in 0 v v in ov dd ?10 a lsync_in upm mode input signal: lupwait t lbixkh2 t lbivkh2 t lbivkh1 t lbixkh1 t lbkhoz1 t1 t3 input signals: lad[0:31]/ldp[0:3] upm mode output signals: lcs [0:3]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:3]/lwe t lbkhov1 t lbkhov1 t lbkhoz1 t2 t4
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 46 freescale semiconductor jtag 10.2 jtag ac electrical characteristics this section describes the ac electrical specificati ons for the ieee 1149.1 (jtag) interface of the device. table 42 provides the jtag ac timing specifications as defined in figure 29 through figure 32 . table 42. jtag ac timing specifications (independent of clkin) 1 at recommended operating conditions (see ta b l e 2 ). parameter symbol 2 min max unit notes jtag external clock frequency of operation f jtg 0 33.3 mhz ? jtag external clock cycle time t jtg 30 ? ns ? jtag external clock duty cycle t jtkhkl /t jtg 45 55 % ? jtag external clock rise and fall times t jtgr & t jtgf 02ns? trst assert time t trst 25 ? ns 3 input setup times: boundary-scan data tms, tdi t jtdvkh t jtivkh 4 4 ? ? ns 4 input hold times: boundary-scan data tms, tdi t jtdxkh t jtixkh 10 10 ? ? ns 4 valid times: boundary-scan data tdo t jtkldv t jtklov 2 2 11 11 ns 5 output hold times: boundary-scan data tdo t jtkldx t jtklox 2 2 ? ? ns 5 jtag external clock to output high impedance: boundary-scan data tdo t jtkldz t jtkloz 2 2 19 9 ns 5, 6 6 notes: 1. all outputs are measured from the midpoint voltage of the falling/rising edge of t tclk to the midpoint of the signal in question. the output timings are measured at the pins. all output timings assume a purely resistive 50- load (see figure 21 ). time-of-flight delays must be added for trace lengths, vias, and connectors in the system. 2. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t jtdvkh symbolizes jtag device timing (jt) with respect to the time data input signals (d) reaching the valid state (v) relative to the t jtg clock reference (k) going to the high (h) state or setup time. also, t jtdxkh symbolizes jtag timing (jt) with respect to the time data input signals (d) went invalid (x) relative to the t jtg clock reference (k) going to the high (h) state. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 3. trst is an asynchronous level sensitive signal. the setup time is for test purposes only. 4. non-jtag signal input timing with respect to t tclk . 5. non-jtag signal output timing with respect to t tclk . 6. guaranteed by design and characterization.
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 freescale semiconductor 47 jtag figure 28 provides the ac test load for tdo and the boundary-scan outputs of the device. figure 28. ac test load for the jtag interface figure 29 provides the jtag clock input timing diagram. figure 29. jtag clock input timing diagram figure 30 provides the trst timing diagram. figure 30. trst timing diagram figure 31 provides the boundary-scan timing diagram. figure 31. boundary-scan timing diagram output z 0 = 50 ov dd /2 r l = 50 jtag t jtkhkl t jtgr external clock vm vm vm t jtg t jtgf vm = midpoint voltage (ov dd /2) trst vm = midpoint voltage (ov dd /2) vm vm t trst vm = midpoint voltage (ov dd /2) vm vm t jtdvkh t jtdxkh boundary data outputs boundary data outputs jtag external clock boundary data inputs output data valid t jtkldx t jtkldz t jtkldv input data valid output data valid
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 48 freescale semiconductor jtag figure 32 provides the test access port timing diagram. figure 32. test access port timing diagram vm = midpoint voltage (ov dd /2) vm vm t jtivkh t jtixkh jtag external clock output data valid t jtklox t jtkloz t jtklov input data valid output data valid tdi, tms tdo tdo
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 freescale semiconductor 49 i 2 c 11 i 2 c this section describes the dc and ac electrical characteristics for the i 2 c interface of the mpc8358e. 11.1 i 2 c dc electrical characteristics table 43 provides the dc electrical characteristics for the i 2 c interface of the device. 11.2 i 2 c ac electrical specifications table 44 provides the ac timing parameters for the i 2 c interface of the device. table 43. i 2 c dc electrical characteristics at recommended operating conditions with ov dd of 3.3 v 10%. parameter symbol min max unit notes input high voltage level v ih 0.7 ov dd ov dd + 0.3 v ? input low voltage level v il ?0.3 0.3 ov dd v? low level output voltage v ol 00.4v1 output fall time from v ih (min) to v il (max) with a bus capacitance from 10 to 400 pf t i2klkv 20 + 0.1 c b 250 ns 2 pulse width of spikes which must be suppressed by the input filter t i2khkl 050ns3 capacitance for each i/o pin c i ?10pf? input current (0 v v in ov dd )i in ?10 a4 notes: 1. output voltage (open drain or open collector) condition = 3 ma sink current. 2. c b = capacitance of one bus line in pf. 3. refer to the mpc8360e integrated communications processor family reference manual for information on the digital filter used. 4. i/o pins will obstruct the sda and scl lines if ov dd is switched off. table 44. i 2 c ac electrical specifications all values refer to v ih (min) and v il (max) levels (see ta b l e 4 3 ). parameter symbol 1 min max unit scl clock frequency f i2c 0400khz low period of the scl clock t i2cl 1.3 ? s high period of the scl clock t i2ch 0.6 ? s setup time for a repeated start condition t i2svkh 0.6 ? s hold time (repeated) start condition (after this period, the first clock pulse is generated) t i2sxkl 0.6 ? s data setup time t i2dvkh 100 ? ns
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 50 freescale semiconductor i 2 c figure 33 provides the ac test load for the i 2 c. figure 33. i 2 c ac test load figure 34 shows the ac timing diagram for the i 2 c bus. figure 34. i 2 c bus ac timing diagram data hold time: cbus compatible masters i 2 c bus devices t i2dxkl ? 0 2 ? 0.9 3 s rise time of both sda and scl signals t i2cr 20 + 0.1 c b 4 300 ns fall time of both sda and scl signals t i2cf 20 + 0.1 c b 4 300 ns set-up time for stop condition t i2pvkh 0.6 ? s bus free time between a stop and start condition t i2khdx 1.3 ? s noise margin at the low level for each connected device (including hysteresis) v nl 0.1 ov dd ?v noise margin at the high level for each connected device (including hysteresis) v nh 0.2 ov dd ?v notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t i2dvkh symbolizes i 2 c timing (i2) with respect to the time data input signals (d) reach the valid state (v) relative to the t i2c clock reference (k) going to the high (h) state or setup time. also, t i2sxkl symbolizes i 2 c timing (i2) for the time that the data with respect to the start condition (s) went invalid (x) relative to the t i2c clock reference (k) going to the low (l) state or hold time. also, t i2pvkh symbolizes i 2 c timing (i2) for the time that the data with respect to the stop condition (p) reaching the valid state (v) relative to the t i2c clock reference (k) going to the high (h) state or setup time. for rise and fall times, the latter convention is used with the approp riate letter: r (rise) or f (fall). 2. the device provides a hold time of at least 300 ns for the sda signal (referred to the v ih min of the scl signal) to bridge the undefined region of the falling edge of scl. 3. the maximum t i2dvkh has only to be met if the device does not stretch the low period (t i2cl ) of the scl signal. 4. c b = capacitance of one bus line in pf. table 44. i 2 c ac electrical specifications (continued) all values refer to v ih (min) and v il (max) levels (see ta b l e 4 3 ). parameter symbol 1 min max unit output z 0 = 50 ov dd /2 r l = 50 sr s sda scl t i2cf t i2sxkl t i2cl t i2ch t i2dxkl t i2dvkh t i2sxkl t i2svkh t i2khkl t i2pvkh t i2cr t i2cf ps
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 freescale semiconductor 51 pci 12 pci this section describes the dc and ac electrical specifications for the pci bus of the mpc8358e. 12.1 pci dc electrical characteristics table 45 provides the dc electrical characteristics for the pci interface of the device. 12.2 pci ac electrical specifications this section describes the general ac timing parameters of the pci bus of the device. note that the pci_clk or pci_sync_in signal is used as the pci input clock depending on whether the device is configured as a host or agent device. table 46 provides the pci ac timing specifications at 66 mhz. . table 45. pci dc electrical characteristics parameter symbol test condition min max unit high-level input voltage v ih v out v oh (min) or 0.5 ov dd ov dd + 0.5 v low-level input voltage v il v out v ol (max) -0.5 0.3 ov dd v high-level output voltage v oh i oh = ?500 a0.9 ov dd ?v low-level output voltage v ol i ol = 1500 a?0.1 ov dd v input current i in 0 v v in 1 ov dd ?10 a note: 1. note that the symbol v in , in this case, represents the ov in symbol referenced in ta b l e 1 and ta b l e 2 . table 46. pci ac timing specifications at 66 mhz parameter symbol 1 min max unit notes clock to output valid t pckhov ?6.0ns2 output hold from clock t pckhox 1?ns2 clock to output high impedance t pckhoz ?14ns2, 3 input setup to clock t pcivkh 3.0 ? ns 2, 4 input hold from clock t pcixkh 0.3 ? ns 2, 4 notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t pcivkh symbolizes pci timing (pc) with respect to the time the input signals (i) reach the valid state (v) relative to the pci_sync_in clock, t sys , reference (k) going to the high (h) state or setup time. also, t pcrhfv symbolizes pci timing (pc) with respect to the time hard reset (r) went high (h) relative to the frame signal (f) going to the valid (v) state. 2. see the timing measurement conditions in the pci 2.2 local bus specifications . 3. for purposes of active/float timing measurements, the hi-z or off-state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 4. input timings are measured at the pin.
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 52 freescale semiconductor pci figure 35 provides the ac test load for pci. figure 35. pci ac test load figure 36 shows the pci input ac timing conditions. figure 36. pci input ac timing measurement conditions table 47. pci ac timing specifications at 33 mhz parameter symbol 1 min max unit notes clock to output valid t pckhov ?11ns2 output hold from clock t pckhox 2?ns2 clock to output high impedance t pckhoz ?14ns2, 3 input setup to clock t pcivkh 7.0 ? ns 2, 4 input hold from clock t pcixkh 0.3 ? ns 2, 4 notes: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t pcivkh symbolizes pci timing (pc) with respect to the time the input signals (i) reach the valid state (v) relative to the pci_sync_in clock, t sys , reference (k) going to the high (h) state or setup time. also, t pcrhfv symbolizes pci timing (pc) with respect to the time hard reset (r) went high (h) relative to the frame signal (f) going to the valid (v) state. 2. see the timing measurement conditions in the pci 2.2 local bus specifications . 3. for purposes of active/float timing measurements, the hi-z or off-state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 4. input timings are measured at the pin. output z 0 = 50 ov dd /2 r l = 50
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 freescale semiconductor 53 timers figure 37 shows the pci output ac timing conditions. figure 37. pci output ac timing measurement condition 13 timers this section describes the dc and ac electrical specifications for the timers of the mpc8358e. 13.1 timers dc electrical characteristics table 48 provides the dc electrical characteristics for the device timer pins, including tin, tout , tgate , and rtc_clk. 13.2 timers ac timing specifications table 49 provides the timer input and output ac timing specifications. table 48. timers dc electrical characteristics characteristic symbol condition min max unit output high voltage v oh i oh = ?6.0 ma 2.4 ? v output low voltage v ol i ol = 6.0 ma ? 0.5 v output low voltage v ol i ol = 3.2 ma ? 0.4 v input high voltage v ih ?2.0ov dd + 0.3 v input low voltage v il ? ?0.3 0.8 v input current i in 0 v v in ov dd ?10 a table 49. timers input ac timing specifications 1 characteristic symbol 2 typ unit timers inputs?minimum pulse width t tiwid 20 ns notes: 1. input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of clkin. timings are measured at the pin. 2. timers inputs and outputs are asynchronous to any visible clock. timers outputs should be synchronized before use by any external synchronous logic. timers inputs are required to be valid for at least t tiwid ns to ensure proper operation. clk output delay t pckhov high-impedance t pckhoz output t pckhox
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 54 freescale semiconductor gpio figure 38 provides the ac test load for the timers. figure 38. timers ac test load 14 gpio this section describes the dc and ac electrical specifications for the gpio of the mpc8358e. 14.1 gpio dc electrical characteristics table 50 provides the dc electrical characteristics for the device gpio. 14.2 gpio ac timing specifications table 51 provides the gpio input and output ac timing specifications. table 50. gpio dc electrical characteristics characteristic symbol condition min max unit notes output high voltage v oh i oh = ?6.0 ma 2.4 ? v 1 output low voltage v ol i ol = 6.0 ma ? 0.5 v 1 output low voltage v ol i ol = 3.2 ma ? 0.4 v 1 input high voltage v ih ?2.0ov dd + 0.3 v 1 input low voltage v il ? ?0.3 0.8 v ? input current i in 0 v v in ov dd ?10 a? note: this specification applies when operating from 3.3-v supply. table 51. gpio input ac timing specifications 1 characteristic symbol 2 typ unit gpio inputs?minimum pulse width t piwid 20 ns notes: 1. input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of clkin. timings are measured at the pin. 2. gpio inputs and outputs are asynchronous to any visible clock. gpio outputs should be synchronized before use by any external synchronous logic. gpio inputs are required to be valid for at least t piwid ns to ensure proper operation. output z 0 = 50 ov dd /2 r l = 50
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 freescale semiconductor 55 ipic figure 39 provides the ac test load for the gpio. figure 39. gpio ac test load 15 ipic this section describes the dc and ac electrical speci fications for the external interrupt pins of the mpc8358e. 15.1 ipic dc electrical characteristics table 52 provides the dc electrical characteristics for the external interrupt pins of the ipic. 15.2 ipic ac timing specifications table 53 provides the ipic input and output ac timing specifications. 16 spi this section describes the dc and ac electrical specifications for the spi of the mpc8358e. table 52. ipic dc electrical characteristics characteristic symbol condition min max unit input high voltage v ih ?2.0ov dd + 0.3 v input low voltage v il ? ?0.3 0.8 v input current i in ??10 a output low voltage v ol i ol = 6.0 ma ? 0.5 v output low voltage v ol i ol = 3.2 ma ? 0.4 v notes: 1. this table applies for pins irq [0:7], irq_out , mcp_out , and ce ports interrupts. 2. irq_out and mcp_out are open drain pins, thus v oh is not relevant for those pins. table 53. ipic input ac timing specifications 1 characteristic symbol 2 min unit ipic inputs?minimum pulse width t piwid 20 ns notes: 1. input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of clkin. timings are measured at the pin. 2. ipic inputs and outputs are asynchronous to any visible clock. ipic outputs should be synchronized before use by any external synchronous logic. ipic inputs are required to be valid for at least t piwid ns to ensure proper operation when working in edge triggered mode. output z 0 = 50 ov dd /2 r l = 50
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 56 freescale semiconductor spi 16.1 spi dc electrical characteristics table 54 provides the dc electrical characteristics for the device spi. 16.2 spi ac timing specifications table 55 and provide the spi input and output ac timing specifications. figure 40 provides the ac test load for the spi. figure 40. spi ac test load table 54. spi dc electrical characteristics characteristic symbol condition min max unit output high voltage v oh i oh = ?6.0 ma 2.4 ? v output low voltage v ol i ol = 6.0 ma ? 0.5 v output low voltage v ol i ol = 3.2 ma ? 0.4 v input high voltage v ih ?2.0ov dd + 0.3 v input low voltage v il ? ?0.3 0.8 v input current i in 0 v v in ov dd ?10 a table 55. spi ac timing specifications 1 characteristic symbol 2 min max unit spi outputs?master mode (internal clock) delay t nikhox t nikhov 0.4 ? ? 8 ns spi outputs?slave mode (external clock) delay t nekhox t nekhov 2 ? ? 8 ns spi inputs?master mode (internal clock) input setup time t niivkh 8?ns spi inputs?master mode (internal clock) input hold time t niixkh 0?ns spi inputs?slave mode (external clock) input setup time t neivkh 4?ns spi inputs?slave mode (external clock) input hold time t neixkh 2?ns notes: 1. output specifications are measured from the 50% level of the rising edge of clkin to the 50% level of the signal. timings are measured at the pin. 2. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t nikhov symbolizes the nmsi outputs internal timing (ni) for the time t spi memory clock reference (k) goes from the high state (h) until outputs (o) are valid (v). output z 0 = 50 ov dd /2 r l = 50
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 freescale semiconductor 57 tdm/si figure 41 and figure 42 represent the ac timing from table 55 . note that although the specifications generally reference the rising edge of the clock, these ac timing diagrams also apply when the falling edge is the active edge. figure 41 shows the spi timing in slave mode (external clock). figure 41. spi ac timing in slave mode (external clock) diagram figure 42 shows the spi timing in master mode (internal clock). figure 42. spi ac timing in master mode (internal clock) diagram 17 tdm/si this section describes the dc and ac electrical specifications for the time-division-multiplexed and serial interface of the mpc8358e. 17.1 tdm/si dc electrical characteristics table 56 provides the dc electrical characteristics for the device tdm/si. table 56. tdm/si dc electrical characteristics characteristic symbol condition min max unit output high voltage v oh i oh = ?2.0 ma 2.4 ? v output low voltage v ol i ol = 3.2 ma ? 0.5 v input high voltage v ih ?2.0ov dd + 0.3 v spiclk (input) t neixkh t neivkh t nekhov input signals: spimosi (see note) output signals: spimiso (see note) note: the clock edge is selectable on spi. spiclk (output) t niixkh t nikhov input signals: spimiso (see note) output signals: spimosi (see note) note: the clock edge is selectable on spi. t niivkh
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 58 freescale semiconductor tdm/si 17.2 tdm/si ac timing specifications table 57 provides the tdm/si input and output ac timing specifications. figure 43 provides the ac test load for the tdm/si. figure 43. tdm/si ac test load figure 44 represents the ac timing from table 55 . note that although the specifications generally reference the rising edge of the clock, these ac timing diagrams also apply when the falling edge is the active edge. input low voltage v il ? ?0.3 0.8 v input current i in 0 v v in ov dd ?10 a table 57. tdm/si ac timing specifications 1 characteristic symbol 2 min max 3 unit tdm/si outputs?external clock delay t sekhov 210ns tdm/si outputs?external clock high impedance t sekhox 210ns tdm/si inputs?external clock input setup time t seivkh 5?ns tdm/si inputs?external clock input hold time t seixkh 2?ns notes: 1. output specifications are measured from the 50% level of the rising edge of clkin to the 50% level of the signal. timings are measured at the pin. 2. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t sekhox symbolizes the tdm/si outputs external timing (se) for the time t tdm/si memory clock reference (k) goes from the high state (h) until outputs (o) are invalid (x). 3. timings are measured from the positive or negative edge of the clock, according to sixmr [ce] and sitxcei[txceix]. see the mpc8360e integrated communications processor family reference manual for more details. table 56. tdm/si dc electrical characteristics (continued) characteristic symbol condition min max unit output z 0 = 50 ov dd /2 r l = 50
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 freescale semiconductor 59 utopia/pos figure 44 shows the tdm/si timing with external clock. figure 44. tdm/si ac timing (external clock) diagram 18 utopia/pos this section describes the dc and ac electrical specifications for the utopia/pos of the mpc8358e. 18.1 utopia/pos dc electrical characteristics table 58 provides the dc electrical characteristics for the device utopia. 18.2 utopia/pos ac timing specifications table 59 provides the utopia input and output ac timing specifications. table 58. utopia dc electrical characteristics characteristic symbol condition min max unit output high voltage v oh i oh = ?8.0 ma 2.4 ? v output low voltage v ol i ol = 8.0 ma ? 0.5 v input high voltage v ih ?2.0ov dd + 0.3 v input low voltage v il ? ?0.3 0.8 v input current i in 0 v v in ov dd ?10 a table 59. utopia ac timing specifications 1 characteristic symbol 2 min max unit notes utopia outputs?internal clock delay t uikhov 0 11.5 ns ? utopia outputs?external clock delay t uekhov 1 11.6 ns ? utopia outputs?internal clock high impedance t uikhox 08.0ns? utopia outputs?external clock high impedance t uekhox 1 10.0 ns ? utopia inputs?internal clock input setup time t uiivkh 6?ns? tdm/siclk (input) t seixkh t seivkh t sekhov input signals: tdm/si (see note) output signals: tdm/si (see note) t sekhox note: the clock edge is selectable on tdm/si
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 60 freescale semiconductor utopia/pos figure 45 provides the ac test load for the utopia. figure 45. utopia ac test load figure 46 and figure 47 represent the ac timing from table 55 . note that although the specifications generally reference the rising edge of the clock, these ac timing diagrams also apply when the falling edge is the active edge. figure 46 shows the utopia timing with external clock. figure 46. utopia ac timing (external clock) diagram utopia inputs?external clock input setup time t ueivkh 4.2 ? ns ? utopia inputs?internal clock input hold time t uiixkh 2.4 ? ns ? utopia inputs?external clock input hold time t ueixkh 1?ns? notes: 1. output specifications are measured from the 50% level of the rising edge of clkin to the 50% level of the signal. timings are measured at the pin. 2. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t uikhox symbolizes the utopia outputs internal timing (ui) for the time t utopia memory clock reference (k) goes from the high state (h) until outputs (o) are invalid (x). table 59. utopia ac timing specifications 1 (continued) characteristic symbol 2 min max unit notes output z 0 = 50 ov dd /2 r l = 50 utopiaclk (input) t ueixkh t ueivkh t uekhov input signals: utopia output signals: utopia t uekhox
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 freescale semiconductor 61 hdlc, bisync, transparent, and synchronous uart figure 47 shows the utopia timing with internal clock. figure 47. utopia ac timing (internal clock) diagram 19 hdlc, bisync, transparent, and synchronous uart this section describes the dc and ac electrical speci fications for the high level data link control (hdlc), bisync, transparent, and synchronous uart protocols of the mpc8358e. 19.1 hdlc, bisync, transparent, and synchronous uart dc electrical characteristics table 60 provides the dc electrical characteristics for the device hdlc, bisync, transparent, and synchronous uart protocols. table 60. hdlc, bisync, transparent, and synchronous uart dc electrical characteristics characteristic symbol condition min max unit output high voltage v oh i oh = ?2.0 ma 2.4 ? v output low voltage v ol i ol = 3.2 ma ? 0.5 v input high voltage v ih ?2.0ov dd + 0.3 v input low voltage v il ? ?0.3 0.8 v input current i in 0 v v in ov dd ?10 a utopiaclk (output) t uiixkh t uikhov input signals: utopia output signals: utopia t uiivkh t uikhox
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 62 freescale semiconductor hdlc, bisync, transparent, and synchronous uart 19.2 hdlc, bisync, transparent, and synchronous uart ac timing specifications table 61 and table 62 provide the input and output ac timing specifications for hdlc, bisync, transparent, and synchronous uart protocols. table 61. hdlc, bisync, and transparent ac timing specifications 1 characteristic symbol 2 min max unit outputs?internal clock delay t hikhov 0 11.2 ns outputs?external clock delay t hekhov 1 10.8 ns outputs?internal clock high impedance t hikhox -0.5 5.5 ns outputs?external clock high impedance t hekhox 18ns inputs?internal clock input setup time t hiivkh 8.5 ? ns inputs?external clock input setup time t heivkh 4?ns inputs?internal clock input hold time t hiixkh 1.4 ? ns inputs?external clock input hold time t heixkh 1?ns notes: 1. output specifications are measured from the 50% level of the rising edge of clkin to the 50% level of the signal. timings are measured at the pin. 2. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t hikhox symbolizes the outputs internal timing (hi) for the time t serial memory clock reference (k) goes from the high state (h) until outputs (o) are invalid (x). table 62. synchronous uart ac timing specifications 1 characteristic symbol 2 min max unit outputs?internal clock delay t uaikhov 0 11.3 ns outputs?external clock delay t uaekhov 114ns outputs?internal clock high impedance t uaikhox 011ns outputs?external clock high impedance t uaekhox 114ns inputs?internal clock input setup time t uaiivkh 6?ns inputs?external clock input setup time t uaeivkh 8?ns inputs?internal clock input hold time t uaiixkh 1?ns inputs?external clock input hold time t uaeixkh 1?ns notes: 1. output specifications are measured from the 50% level of the rising edge of clkin to the 50% level of the signal. timings are measured at the pin. 2. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t hikhox symbolizes the outputs internal timing (hi) for the time t serial memory clock reference (k) goes from the high state (h) until outputs (o) are invalid (x).
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 freescale semiconductor 63 hdlc, bisync, transparent, and synchronous uart figure 48 provides the ac test load. figure 48. ac test load 19.3 ac test load figure 49 and figure 50 represent the ac timing from table 61 and table 62 . note that although the specifications generally reference the rising edge of the clock, these ac timing diagrams also apply when the falling edge is the active edge. figure 49 shows the timing with external clock. figure 49. ac timing (external clock) diagram figure 50 shows the timing with internal clock. figure 50. ac timing (internal clock) diagram output z 0 = 50 ov dd /2 r l = 50 serial clk (input) t heixkh t heivkh t hekhov input signals: (see note) output signals: (see note) t hekhox note: the clock edge is selectable. serial clk (output) t hiixkh thikhov input signals: (see note) t hiivkh t hikhox note: the clock edge is selectable. output signals: (see note)
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 64 freescale semiconductor usb 20 usb this section provides the ac and dc electrical sp ecifications for the usb interface of the mpc8358e. 20.1 usb dc electrical characteristics table 63 provides the dc electrical characteristics for the usb interface. 20.2 usb ac electrical specifications table 64 describes the general timing parameters of the usb interface of the device. figure 51 provide the ac test load for the usb. figure 51. usb ac test load table 63. usb dc electrical characteristics parameter symbol min max unit high-level input voltage v ih 2ov dd + 0.3 v low-level input voltage v il ?0.3 0.8 v high-level output voltage, i oh = ?100 av oh ov dd ? 0.4 ? v low-level output voltage, i ol = 100 av ol ?0.2v input current i in ?10 a table 64. usb general timing parameters parameter symbol 1 min max unit notes usb clock cycle time t usck 20.83 ? ns full speed 48 mhz usb clock cycle time t usck 166.67 ? ns low speed 6 mhz skew between txp and txn t ustspn ?5ns? skew among rxp, rxn, and rxd t usrspnd ? 10 ns full speed transitions skew among rxp, rxn, and rxd t usrpnd ? 100 ns low speed transitions notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(state)(signal) for receive signals and t (first two letters of functional block)(state)(signal) for transmit signals. for example, t usrspnd symbolizes usb timing (us) for the usb receive signals skew (rs) among rxp, rxn, and rxd (pnd). also, t ustspn symbolizes usb timing (us) for the usb transmit signals skew (ts) between txp and txn (pn). 2.skew measurements are done at ov dd /2 of the rising or falling edge of the signals. output z 0 = 50 ov dd /2 r l = 50
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 freescale semiconductor 65 package and pin listings 21 package and pin listings this section details package parameters, pin assignmen ts, and dimensions. the mpc8358e is available in a plastic ball grid array (pbga), see section 21.1, ?package parameters for the pbga package ,? and section 21.2, ?mechanical dimensions of the pbga package ,? for information on the package. 21.1 package parameters for the pbga package the package parameters for rev 2.0 silicon are as provided in the following list. the package type is 2 9 mm x 29 mm, 668 plastic ball grid array (pbga). package outline 29 mm x 29 mm interconnects 668 pitch 1.00 mm module height (typical) 1.46 mm solder balls 62 sn/36 pb/2 ag ( zq package) 95.5 sn/0.5 cu/4ag (vr package) ball diameter (typical) 0.64 mm
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 66 freescale semiconductor package and pin listings 21.2 mechanical dimensions of the pbga package figure 52 depicts the mechanical dimensions and bottom surface nomenclature of the 668-pbga package. figure 52. mechanical dimensions and bottom surface nomenclature of the pbga package notes: 1. all dimensions are in millimeters. 2. dimensions and tolerances per asme y14.5m-1994. 3. maximum solder ball diameter measured parallel to datum a.
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 freescale semiconductor 67 package and pin listings 4. datum a, the seating plane, is determined by the spherical crowns of the solder balls. 5. parallelism measurement must exclude any effect of mark on top surface of package. 6. distance from the seating plane to the encapsulant material. 21.3 pinout listings refer to an3097, ?mpc8360/mpc8358e powerquicc design checklist,? for proper pin termination and usage. table 65 shows the pin list of the mpc8358e pbga package. table 65. mpc8358e pbga pinout listing signal package pin number pin type power supply notes ddr sdram memory controller interface memc_mdq[0:63] ad20, ag24, af24, ah24, af23, ae22, ah26, ad21, ah25, ad22, af27, ab24, ag25, ac22, ae25, ac24, ad25, ab25, ac25, ag28, ad26, ae23, ag26, ac26, ad27, v25, aa28, aa25, y26, w27, u24, w24, e28, h24, e26, d25, g27, h25, g26, f26, f27, f25, d26, f24, g25, e27, d27, c28, c27, f22, b26, f21, b28, e22, d24, c24, a25, e20, f20, d20, a23, c21, c23, e19 i/o gv dd ? memc_mecc[0:7] n26, n24, j26, h28, n28, p24, l26, k24 i/o gv dd ? memc_mdm[0:8] ag23, ad23, ae26, v28, g28, d28, d23, b24, u27 o gv dd ? memc_mdqs[0:8] ah23, ah27, af28, t28, h26, e25, b25, a24, r28 i/o gv dd ? memc_mba[0:2] v26, w28, y28 o gv dd ? memc_ma[0:14] l25, m25, m24, k28, p28, t24, m27, r25, p25, l28, u26, m28, l27, k27, h27 ogv dd ? memc_modt[0:3] ae21, ac19, e23, b23 ? gv dd 6 memc_mwe r27 o gv dd ? memc_mras w25 o gv dd ? memc_mcas r24 o gv dd ? memc_mcs [0:3] t26, u28, j25, f28 o gv dd ? memc_mcke[0:1] ad24, ae28 o gv dd ? memc_mck[0:5] ag22, ag27, a26, c26, p26, e21 o gv dd ? memc_mck [0:5] af22, af26, a27, b27, n27, d22 o gv dd ? mdic[0:1] f19, aa27 i/o gv dd 11 pci pci_inta / pf[5] r3 i/o lv dd 22 pci_reset_out / pf[6] p6 i/o lv dd 2? pci_ad[0:31]/ pg[0:31] ab5, ac5, ag1, aa5, af2, ad4, y6, af1, ae2, ac4, ad3, ae1, y4, ac3, ad2, ad1, ab2, y3, aa1, y1, w1, v6, w3, v4, t5, w2, v5, v1, u4, v2, u2, t2 i/o lv dd 2? pci_c_be [0:3]/ pf[7:10] y5, ac2, y2, u5 i/o ov dd ?
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 68 freescale semiconductor package and pin listings pci_par/ pf[11] aa4 i/o ov dd ? pci_frame / pf[12] w4 i/o ov dd 5 pci_trdy / pf[13] w5 i/o ov dd 5 pci_irdy / pf[14] ab3 i/o ov dd 5 pci_stop / pf[15] ab1 i/o ov dd 5 pci_devsel / pf[16] aa2 i/o ov dd 5 pci_idsel/ pf[17] u6 i/o ov dd ? pci_serr / pf[18] ac1 i/o ov dd 5 pci_perr / pf[19] w6 i/o ov dd 5 pci_req [0:2]/ pf[20:22] r2, t4, u1 i/o lv dd 2? pci_gnt [0:2]/ pf[23:25] t3, r5, t1 i/o lv dd 2? pci_mode ae5 i ov dd ? m66en/ ce_pf[4] ah3 i/o ov dd ? local bus controller interface lad[0:31] ac11, ae10, ad10, ad11, ae11, ag11, ah11, ah12, ag12, af12, ad12, ae12, ac12, ah13, ag13, af13, ae13, ah14, ad13, ag14, af14, ah15, ae14, ag15, ac13, ad14, ac14, ah16, ac15, ag16, ae15, af16 i/o ov dd ? ldp[0:3] ad15, ag17, ac16, af17 i/o ov dd ? la[27:31] ah17, ad16, ah18, ag18, ae17 o ov dd ? lcs [0:5] ad18, ah20, ag20, ae19, ac18, ah21 o ov dd ? lwe [0:3] ag21, ah22, ac20, ad19 o ov dd ? lbctl af18 o ov dd ? lale af10 o ov dd ? lgpl0/ lsda10/ cfg_reset_source0 ac17 i/o ov dd ? lgpl1/ lsdwe/ cfg_reset_source1 ad17 i/o ov dd ? table 65. mpc8358e pbga pinout listing (continued) signal package pin number pin type power supply notes
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 freescale semiconductor 69 package and pin listings lgpl2/ lsdras / loe ah19 o ov dd ? lgpl3/ lsdcas/ cfg_reset_source2 ae18 i/o ov dd ? lgpl4/ lgta / lupwait/ lpbse ag19 i/o ov dd ? lgpl5/ cfg_clkin_div af19 i/o ov dd ? lcke ad8 o ov dd ? lclk[0] ac9 o ov dd ? lclk[1]/ lcs[6] ag6 o ov dd ? lclk[2]/ lcs[7] ae7 o ov dd ? lsync_out ag4 o ov dd ? lsync_in ac8 i ov dd ? programmable interrupt controller mcp_out ag3 o ov dd 2 irq 0/ mcp_in ah4 i ov dd ? irq [1:2] ag5, ah5 i/o ov dd ? irq [3]/ core_sreset ad7 i/o ov dd ? irq [4:5] ac7, ad6 i/o ov dd ? irq [6:7] ac6, ac10 i/o ov dd ? duart uart1_sout ae3 o ov dd ? uart1_sin ae4 i/o ov dd ? uart1_cts ag2 i/o ov dd ? uart1_rts aa6 o ov dd ? i 2 c interface iic1_sda ab6 i/o ov dd 2 iic1_scl ad5 i/o ov dd 2 iic2_sda af3 i/o ov dd 2 iic2_scl ah2 i/o ov dd 2 quicc engine ce_pa[0] f6 i/o lv dd 0? table 65. mpc8358e pbga pinout listing (continued) signal package pin number pin type power supply notes
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 70 freescale semiconductor package and pin listings ce_pa[1:2] a22, c20 i/o ov dd ? ce_pa[3:7] c3, d3, c2, d2, b1 i/o lv dd 0? ce_pa[8] f18 i/o ov dd ? ce_pa[9:12] e3, c1, b2, d1 i/o lv dd 0? ce_pa[13:14] b21, d19 i/o ov dd ? ce_pa[15] e4 i/o lv dd 0? ce_pa[16] e18 i/o ov dd ? ce_pa[17:21] m2, n5, n3, n4, n2 i/o lv dd 1? ce_pa[22] f17 i/o ov dd ? ce_pa[23:26] n1, p1, p2, p4 i/o lv dd 1? ce_pa[27:28] a21, e17 i/o ov dd ? ce_pa[29] p5 i/o lv dd 1? ce_pa[30] b20 i/o ov dd ? ce_pa[31] m4 i/o lv dd 1? ce_pb[0:27] d18, c18, a20, b19, f16, e16, b18, a19, c17, d16, e15, a18, f15, b17, a17, d15, b16, a16, c15, b15, a15, e14, f14, d14, c14, b14, a14, e13 i/o ov dd ? ce_pc[0:1] f13, d13 i/o ov dd ? ce_pc[2:3] n6, m1 i/o lv dd 1? ce_pc[4:6] c13, b13, a13 i/o ov dd ? ce_pc[7] r1 i/o lv dd 2? ce_pc[8:9] f4, e2 i/o lv dd 0? ce_pc[10:30] d12, e12, f12, b12, a12, a11, b11, k5, k6, j1, j2, j3, h1, j4, h6, j5, m5, l1, m3, f5, b22 i/o ov dd ? ce_pd[0:27] h2, h3, g6, g1, h4, h5, g2, g3, f1, j6, f2, g4, e1, g5, b3, a3, d4, c4, a2, e5, b4, f8, a4, d5, c5, b5, e6, e8 i/o ov dd ? ce_pe[0:31] d8, a7, a5, e7, d6, f9, b6, a6, d7, c7, b7, e9, c8, e11, c11, f11, a10, b10, c10, e10, d10, a9, b9, c9, d9, f10, a8, b8, m6, k1, l3, l2 i/o ov dd ? ce_pf[0:3] l6, k2, l5, k4 i/o ov dd ? clocks pci_clk[0]/ pf[26] r6 i/o lv dd 2? pci_clk[1:2]/ pf[27:28] u3, t6 i/o ov dd ? clkin ah6 i ov dd ? pci_sync_in af7 i ov dd ? pci_sync_out/ pf[29] af6 i/o ov dd 3 jtag tck ad9 i ov dd ? table 65. mpc8358e pbga pinout listing (continued) signal package pin number pin type power supply notes
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 freescale semiconductor 71 package and pin listings tdi ae8 i ov dd 4 tdo ag7 o ov dd 3 tms ah7 i ov dd 4 trst ag8 i ov dd 4 test test af9 i ov dd 7 test_sel ae27 i gv dd 9 pmc quiesce af4 o ov dd ? system control poreset ae9 i ov dd ? hreset ag9 i/o ov dd 1 sreset ah10 i/o ov dd 2 thermal management therm0 k25 i gv dd ? therm1 aa26 i gv dd ? power and ground signals av dd 1af8 power for lbiu dll (1.2 v) av dd 1? av dd 2 ah8 power for ce pll (1.2 v) av dd 2? av dd 5 ab26 power for e300 pll (1.2 v) av dd 5? av dd 6 ah9 power for system pll (1.2 v) av dd 6? gnd c16, d11, d21, e24, f7, j10, j12, j15, j16, j17, j28, k11, k13, k14, k17, k18, l4, l9, l11, l12, l13, l14, l15, l16, l17, l18, l19, l24, m10, m11, m14, m15, m18, m19, n11, n18, n25, p9, p11, p18, p19, r9, r11, r14, r15, r18, r19, r26, t10, t11, t14, t15, t18, t25, u10, u11, u18, v9, v11, v14, v15, v18, v24, v27, w18, w19, y11, y14, y18, y19, y25, y27, ab4, ab27, ac27, ae20, ae24, af5, af15, ag10 ??? table 65. mpc8358e pbga pinout listing (continued) signal package pin number pin type power supply notes
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 72 freescale semiconductor package and pin listings gv dd c19, c22, c25, g24, j18, j19, j20, j24, k19, k20, k26, l20, m20, m26, n19, n20, p20, p27, r20, t19, t20, t27, u19, u20, u25, v19, v20, w20, w26, y20, aa24, ab28, ac21, ac28, ad28, af21, af25 power for ddr dram i/o voltage (2.5 v or 1.8 v) gv dd ? lv dd 0f3, j9 ?lv dd 0? lv dd 1p3, p10 ?lv dd 110 lv dd 2r4, r10 ?lv dd 210 v dd m12, m13, m16, m17, n10, n12, n13, n14, n15, n16, n17, p12, p13, p14, p15, p16, p17, r12, r13, r16, r17, t12, t13, t16, t17, u12, u13, u14, u15, u16, u17, v12, v13, v16, v17, w11, w12, w13, w15, w16, w17, y16, y17 power for core (1.2 v) v dd ? ov dd c6, c12, d17, j11, j13, j14, k3, k9, k10, k12, k15, k16, l10, m9, n9, t9, u9, v3, v10, w9, w10, w14, y9, y10, y12, y13, y15, aa3, ae6, ae16, af11, af20 pci, 10/100 ethernet, and other standard (3.3 v) ov dd ? mvref1 j27 i ddr referenc e voltage ? mvref2 y24 i ddr referenc e voltage ? no connect nc f23, g23, h23, j23, k23, l23, m23, n23, p23, r23, t23, u23, v23, w23, y23, aa23, ab23, ac23 ??? notes: 1. this pin is an open drain signal. a weak pull-up resistor (1 k ) should be placed on this pin to ov dd . 2. this pin is an open drain signal. a weak pull-up resistor (2?10 k ) should be placed on this pin to ov dd. 3. this output is actively driven during reset rather than being three-stated during reset. 4. these jtag pins have weak internal pull-up p-fets that are always enabled. 5.this pin should have a weak pull up if the chip is in pci host mode. follow pci specifications recommendation. 6. these are on die termination pins, used to control ddr2 memories internal termination resistance. 7. this pin must always be tied to gnd. 8. this pin must always be left not connected. 9. this pin must always be tied to gv dd . 10. refers to mpc8360e powerquicc ii? pro integrated communications processor reference manual section on ?rgmii pins? for information about the two ucc2 ethernet interface options. 11. it is recommended that mdic0 be tied to gnd using an 18.2 resistor and mdic1 be tied to ddr power using an 18.2 resistor for ddr2. table 65. mpc8358e pbga pinout listing (continued) signal package pin number pin type power supply notes
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 freescale semiconductor 73 clocking 22 clocking figure 53 shows the internal distribution of clocks within the mpc8358e. figure 53. mpc8358e clock subsystem the primary clock source for the device can be one of two inputs, clkin or pci_clk, depending on whether the device is configured in pci host or pci agent mode. note that in pci host mode, the primary clock input also depends on whether pci clock output s are selected with rcwh[pcickdrv]. when the device is configured as a pci host device (rcwh[ pcihost] = 1) and pci clock output is selected (rcwh[pcickdrv] = 1), clkin is its primary input clock. clkin feeds the pci clock divider ( 2) and the multiplexors for pci_sync_out and pci_clk_out. the cfg_clkin_div configuration core pll system lbiu lsync_in lsync_out lclk[0:2] core_clk e300 core csb_clk to rest clkin csb_clk mpc8358e local bus pci_clk_out[0:2] pci_sync_out pci_clk/ clock unit of the device lb_clk cfg_clkin_div pci clock pci_sync_in memory device /n dll divider memc1_mck[0:5] memc1_mck [0:5] ddrc /2 ddr1_clk ddrc memory device pll quicc pll ce_clk to quicc engine block engine
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 74 freescale semiconductor clocking input selects whether clkin or clkin/2 is driven out on the pci_sync_out signal. the occr[pcioen n ] parameters enable the pci_clk_out n , respectively. pci_sync_out is connected externally to pci_s ync_in to allow the internal clock subystem to synchronize to the system pci clocks. pci_sync_out must be connected properly to pci_sync_in, with equal delay to all pci agent devices in the system, to allow the device to function. when the device is configured as a pci agent device, pci_clk is the primary input clock. when the device is configured as a pci agent device the clkin and the cfg_clkin_div signals should be tied to gnd. when the device is configured as a pci host de vice (rcwh[pcihost] = 1) and pci clock output is disabled (rcwh[pcickdrv] = 0), clock distribut ion and balancing done ex ternally on the board. therefore, pci_sync_in is the primary input clock. as shown in figure 53 , the primary clock input (frequency) is multiplied by the quicc engine block phase-locked loop (pll), the system pll, and the clock unit to create the quicc engine clock ( ce_clk ), the coherent system bus clock ( csb_clk ), the internal ddrc1 controller clock ( ddr1_clk ), and the internal clock for the local bus interface unit and ddr2 memory controller ( lb_clk ). the csb_clk frequency is derived from a complex set of factors that can be simplified into the following equation: csb_clk = {pci_sync_in (1 + cfg_clkin_div)} spmf in pci host mode, pci_sync_in (1 + cfg_clkin_div) is the clkin frequency; in pci agent mode, cfg_clkin_div must be pulled down (low), so pci_sync_in (1 + cfg_clkin_div) is the pci_clk frequency. the csb_clk serves as the clock input to the e300 core. a second pll inside the e300 core multiplies up the csb_clk frequency to create the internal clock for the e300 core ( core_clk ). the system and core pll multipliers are selected by the spmf and corepll fields in the reset configuration word low (rcwl) which is loaded at power-on reset or by one of the hard-coded reset options. see chapter 4, ?reset, clocking, and initialization,? in the mpc8360e powerquicc ii pro integrated communications processor family reference manual for more information on the clock subsystem. the ce_clk frequency is determined by the quicc engine pll multiplication factor (rcwl[cepmf) and the quicc engine pll division factor (rcwl[cepdf]) according to the following equation: ce_clk = (primary clock input cepmf) (1 + cepdf) the internal ddr1_clk frequency is determined by the following equation: ddr1_clk = csb_clk (1 + rcwl[ddr1cm]) note that the lb_clk clock frequency (for ddrc2) is determined by rcwl[lbcm]. the internal ddr1_clk frequency is not the extern al memory bus frequency; ddr1_clk passes through the ddrc1 clock divider ( 2) to create the differential ddrc1 memory bus clock outputs (memc1_mck and memc1_mck ). however, the data rate is the same frequency as ddr1_clk . the internal lb_clk frequency is determined by the following equation: lb_clk = csb_clk (1 + rcwl[lbcm])
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 freescale semiconductor 75 clocking note that lb_clk is not the external local bus or ddrc2 frequency; lb_clk passes through the a lb clock divider to create the external local bus clock outputs (lsync_out and lclk[0:2]). the lb clock divider ratio is controlled by lcrr[clkdiv]. in addition, some of the internal units may be require d to be shut off or operate at lower frequency than the csb_clk frequency. those units have a default clock ra tio that can be configured by a memory mapped register after the device comes out of reset. table 66 specifies which units ha ve a configurable clock frequency. table 67 provides the operating frequencies for th e pbga package under recommended operating conditions (see table 2 ). all frequency combinations shown in the table below may not be available. maximum operating frequencies depend on the part ordered, see section 25.1, ?part numbers fully addressed by this document,? for part ordering details and contact your freescale sales representative or authorized distributor for more information. table 66. configurable clock units unit default frequency options security core csb_clk /3 off, csb_clk 1 , csb_clk /2, csb_clk /3 1 with limitation, only for slow csb_clk rates, up to 166 mhz. pci and dma complex csb_clk off, csb_clk table 67. operating frequencies for the pbga package characteristic 1 1 the clkin frequency, rcwl[spmf], and rcwl[corepll] settings must be chosen such that the resulting csb_clk , mclk, lclk[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. 400 mhz unit e300 core frequency ( core_clk ) 266?400 mhz coherent system bus frequency ( csb_clk ) 133?266 mhz quicc engine frequency ( ce_clk ) 266?400 mhz ddr and ddr2 memory bus frequency (mclk) 2 2 the ddr data rate is 2x the ddr memory bus frequency. 100?133 mhz local bus frequency (lclk n ) 3 3 the local bus frequency is 1/2, 1/4, or 1/8 of the lb_clk frequency (depending on lcrr[clkdiv]) which is in turn 1x or 2x the csb_clk frequency (depending on rcwl[lbcm]). 16.67?133 mhz pci input frequency (clkin or pci_clk) 25?66.67 mhz security core maximum internal operating frequency 133 mhz
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 76 freescale semiconductor clocking 22.1 system pll configuration the system pll is controlled by the rcwl[spmf] and rcwl[svcod] parameters. table 68 shows the multiplication factor encodings for the system pll. the rcwl[svcod] denotes the system pll vco internal frequency as shown in table 69 . note the vco divider must be set properly so that the system vco frequency is in the range of 600?1400 mhz. table 68. system pll multiplication factors rcwl[spmf] system pll multiplication factor 0000 16 0001 reserved 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 10 1011 11 1100 12 1101 13 1110 14 1111 15 table 69. system pll vco divider rcwl[svcod] vco divider 00 4 01 8 10 2 11 reserved
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 freescale semiconductor 77 clocking the system vco frequency is derived from the following equations: ? csb_clk = {pci_sync_in (1 + cfg_clkin_div)} spmf ? system vco frequency = csb_clk vco divider (if both rcwl[ddrcm] and rcwl[lbcm] are cleared) or ? system vco frequency = 2 csb_clk vco divider (if either rcwl[ddrcm] or rcwl[lbcm] are set). as described in section 22, ?clocking,? the lbcm, ddrcm, and spmf parameters in the reset configuration word low and the cfg_clkin_div confi guration input signal select the ratio between the primary clock input (clkin or pci_clk) and the internal coherent system bus clock ( csb_clk ). table 70 shows the expected frequency values for the csb frequency for select csb_clk to clkin/pci_sync_in ratios. table 70. csb frequency options cfg_clkin_div at reset 1 spmf csb_clk : input clock ratio 2 input clock frequency (mhz) 2 16.67 25 33.33 66.67 csb_clk frequency (mhz) low 0010 2:1 133 low 0011 3:1 100 200 low 0100 4:1 100 133 266 low 0101 5:1 125 166 333 low 0110 6:1 100 150 200 low 0111 7:1 116 175 233 low 1000 8:1 133 200 266 low 1001 9:1 150 225 300 low 1010 10:1 166 250 333 low 1011 11:1 183 275 low 1100 12:1 200 300 low 1101 13:1 216 325 low 1110 14:1 233 low 1111 15:1 250 low 0000 16:1 266 high 0010 2:1 133 high 0011 3:1 100 200 high 0100 4:1 133 266 high 0101 5:1 166 333
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 78 freescale semiconductor clocking 22.2 core pll configuration rcwl[corepll] selects the ratio between the internal coherent system bus clock ( csb_clk ) and the e300 core clock ( core_clk ). table 71 shows the encodings for rcwl[corepll]. corepll values not listed in table 71 should be considered reserved. high 0110 6:1 200 high 0111 7:1 233 high 1000 8:1 high 1001 9:1 high 1010 10:1 high 1011 11:1 high 1100 12:1 high 1101 13:1 high 1110 14:1 high 1111 15:1 high 0000 16:1 1 cfg_clkin_div is only used for host mode; clkin must be tied low and cfg_clkin_div must be pulled down (low) in agent mode. 2 clkin is the input clock in host mode; pci_clk is the input clock in agent mode. table 71. e300 core pll configuration rcwl[corepll] core_clk : csb_clk ratio vco divider 0?1 2?5 6 nn 0000 n pll bypassed (pll off, csb_clk clocks core directly) pll bypassed (pll off, csb_clk clocks core directly) 00 0001 01:1 2 01 0001 01:1 4 10 0001 01:1 8 11 0001 01:1 8 00 0001 11.5:1 2 01 0001 11.5:1 4 10 0001 11.5:1 8 table 70. csb frequency options (continued) cfg_clkin_div at reset 1 spmf csb_clk : input clock ratio 2 input clock frequency (mhz) 2 16.67 25 33.33 66.67 csb_clk frequency (mhz)
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 freescale semiconductor 79 clocking note core vco frequency = core frequency vco divider. the vco divider (rcwl[corepll[0:1]]) must be set properly so that the core vco frequency is in the range of 800?1800 mh z. having a core frequency below the csb frequency is not a possible option because the core frequency must be equal to or greater than the csb frequency. 22.3 quicc engine block pll configuration the quicc engine block pll is controlled by the rcwl[cepmf], rcwl[cepdf], and rcwl[cevcod] parameters. table 72 shows the multiplication factor encodings for the quicc engine block pll. 11 0001 11.5:1 8 00 0010 02:1 2 01 0010 02:1 4 10 0010 02:1 8 11 0010 02:1 8 00 0010 12.5:1 2 01 0010 12.5:1 4 10 0010 12.5:1 8 11 0010 12.5:1 8 00 0011 03:1 2 01 0011 03:1 4 10 0011 03:1 8 11 0011 03:1 8 table 72. quicc engine block pll multiplication factors rcwl[cepmf] rcwl[cepdf] quicc engine pll multiplication factor = rcwl[cepmf]/ (1 + rcwl[cepdf]) 00000 0 16 00001 0 reserved 00010 0 2 00011 0 3 00100 0 4 table 71. e300 core pll configuration (continued) rcwl[corepll] core_clk : csb_clk ratio vco divider 0?1 2?5 6
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 80 freescale semiconductor clocking 00101 0 5 00110 0 6 00111 0 7 01000 0 8 01001 0 9 01010 0 10 01011 0 11 01100 0 12 01101 0 13 01110 0 14 01111 0 15 10000 0 16 10001 0 17 10010 0 18 10011 0 19 10100 0 20 10101 0 21 10110 0 22 10111 0 23 11000 0 24 11001 0 25 11010 0 26 11011 0 27 11100 0 28 11101 0 29 11110 0 30 11111 0 31 00011 1 1.5 00101 1 2.5 00111 1 3.5 01001 1 4.5 table 72. quicc engine block pll multiplication factors (continued) rcwl[cepmf] rcwl[cepdf] quicc engine pll multiplication factor = rcwl[cepmf]/ (1 + rcwl[cepdf])
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 freescale semiconductor 81 clocking the rcwl[cevcod] denotes the quicc engine block pll vco internal frequency as shown in table 73 . note the vco divider (rcwl[cevcod]) must be set properly so that the quicc engine block vco frequency is in the range of 600?1400 mhz. the quicc engine block frequency is not restricted by the csb and core frequencies. the csb, core, and qu icc engine block frequencies should be selected according to the performance requirements. the quicc engine block vco frequency is derived from the following equations: ce_clk = (primary clock input cepmf) (1 + cepdf) qe vco frequency = ce_clk vco divider (1 + cepdf) 01011 1 5.5 01101 1 6.5 01111 1 7.5 10001 1 8.5 10011 1 9.5 10101 1 10.5 10111 1 11.5 11001 1 12.5 11011 1 13.5 11101 1 14.5 note: 1. reserved modes are not listed. table 73. quicc engine block pll vco divider rcwl[cevcod] vco divider 00 4 01 8 10 2 11 reserved table 72. quicc engine block pll multiplication factors (continued) rcwl[cepmf] rcwl[cepdf] quicc engine pll multiplication factor = rcwl[cepmf]/ (1 + rcwl[cepdf])
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 82 freescale semiconductor clocking 22.4 suggested pll configurations to simplify the pll configurations, the device might be separated into two clock domains. the first domain contains the csb pll and the core pll. the core pll is connected serially to the csb pll, and has the csb_clk as its input clock. the second clock domain has the quicc engine block pll. the clock domains are independent, and each of their plls are c onfigured separately. both of the domains has one common input clock. table 74 shows suggested pll configurations for 33 and 66 mhz input clocks and illustrates each of the clock domains separately. any combination of clock domains setting with same input clock are valid. refer to section 22, ?clocking,? for the appropriate opera ting frequencies for your device. table 74. suggested pll configurations conf no. 1 spmf core pll cepmf cepdf input clock freq (mhz) csb freq (mhz) core freq (mhz) quicc engine freq (mhz) 400 (mhz) 533 (mhz) 667 (mhz) 33 mhz clkin/pci_sync_in options s1 0100 0000100 ? ? 33 133 266 ? ? s2 0100 0000101 ? ? 33 133 333 ? ? s3 0101 0000100 ? ? 33 166 333 ? ? s4 0101 0000101 ? ? 33 166 416 ? ? ? s5 0110 0000100 ? ? 33 200 400 ? ? s6 0110 0000110 ? ? 33 200 600 ? ? ? s7 0111 0000011 ? ? 33 233 350 ? ? s8 0111 0000100 ? ? 33 233 466 ? ? ? s9 0111 0000101 ? ? 33 233 583 ? ? ? s10 1000 0000011 ? ? 33 266 400 ? ? s11 1000 0000100 ? ? 33 266 533 ? ? ? s12 1000 0000101 ? ? 33 266 667 ? ? ? s13 1001 0000010 ? ? 33 300 300 ? ? s14 1001 0000011 ? ? 33 300 450 ? ? ? s15 1001 0000100 ? ? 33 300 600 ? ? ? s16 1010 0000010 ? ? 33 333 333 ? ? s17 1010 0000011 ? ? 33 333 500 ? ? ? s18 1010 0000100 ? ? 33 333 667 ? ? ? c1 ? ? 01001 0 33 ? ? 300 ? c2 ? ? 01100 0 33 ? ? 400 ? c3 ? ? 01110 0 33 ? ? 466 ? ? c4 ? ? 01111 0 33 ? ? 500 ? ?
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 freescale semiconductor 83 clocking the following steps describe how to use table 74 . see example 1 . 1. choose the up or down sections in the table according to input clock rate 33 mhz or 66 mhz. 2. select a suitable csb and core clock rates from table 74 . copy the spmf and core pll configuration bits. 3. select a suitable quicc engine block clock rate from table 74 . copy the cepmf and cepdf configuration bits. 4. insert the chosen spmf, corepll, cepmf and cepdf to the rcwl fields, respectively. example 1. sample table use c5 ? ? 10000 0 33 ? ? 533 ? ? c6 ? ? 10001 0 33 ? ? 566 ? ? 66 mhz clkin/pci_sync_in options s1h 0011 0000110 ? ? 66 200 400 ? ? s2h 0011 0000101 ? ? 66 200 500 ? ? ? s3h 0011 0000110 ? ? 66 200 600 ? ? ? s4h 0100 0000011 ? ? 66 266 400 ? ? s5h 0100 0000100 ? ? 66 266 533 ? ? ? s6h 0100 0000101 ? ? 66 266 667 ? ? ? s7h 0101 0000010 ? ? 66 333 333 ? ? s8h 0101 0000011 ? ? 66 333 500 ? ? ? s9h 0101 0000100 ? ? 66 333 667 ? ? ? c1h ? ? 00101 0 66 ? ? 333 ? c2h ? ? 00110 0 66 ? ? 400 ? c3h ? ? 00111 0 66 ? ? 466 ? ? c4h ? ? 01000 0 66 ? ? 533 ? ? c5h ? ? 01001 0 66 ? ? 600 ? ? 1 the conf no. consist of prefix, an index and a postfix. the prefix ?s? and ?c? stands for ?syset? and ?ce? respectively. the po stfix ?h? stands for ?high input clock.??the index is a serial number. spmf core pll cepmf cepdf input clock (mhz) csb freq (mhz) core freq (mhz) quicc engine freq (mhz) 400 (mhz) 1000 0000011 01001 0 33 266 400 300 table 74. suggested pll configurations (continued) conf no. 1 spmf core pll cepmf cepdf input clock freq (mhz) csb freq (mhz) core freq (mhz) quicc engine freq (mhz) 400 (mhz) 533 (mhz) 667 (mhz)
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 84 freescale semiconductor thermal ? to configure the device with csb clock rate of 266 mhz, core rate of 400 mhz, and quicc engine clock rate 300 mhz while the input clock rate is 33 mhz. conf no. ?s10? and ?c1? are selected from table 74 . spmf is 1000, corpll is 0000011, cepmf is 01001, and cepdf is 0. 23 thermal this section describes the thermal specifications of the mpc8358e. 23.1 thermal characteristics table 75 provides the package thermal characteristics for the 668 29 mm x 29 mm pbga package. 23.2 thermal management information for the following sections, p d = (v dd i dd ) + p i/o where p i/o is the power dissipation of the i/o drivers. see table 5 for typical power dissipations values. table 75. package thermal characteristics for the pbga package characteristic symbol value unit notes junction-to-ambient natural convection on single layer board (1s) r ja 20 c/w 1, 2 junction-to-ambient natural convection on four layer board (2s2p) r ja 14 c/w 1, 2, 3 junction-to-ambient (@1 m/s) on single layer board (1s) r jma 15 c/w 1, 3 junction-to-ambient (@ 1 m/s) on four layer board (2s2p) r jma 11 ?c/w c/w 1, 3 junction-to-board thermal r jb 6?c/w c/w 4 junction-to-case thermal r jc 4?c/w c/w 5 junction-to-package natural convection on top jt 4?c/w c/w 6 notes 1. junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. per jedec jesd51-2 and jedec jesd51-9 with the single layer board horizontal. 3. per jedec jesd51-6 with the board horizontal. 1 m/sec is approximately equal to 200 linear feet per minute (lfm). 4. thermal resistance between the die and the printed circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 5. thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1). 6. thermal characterization parameter indicating the temperature difference between package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the thermal characterization parameter is written as psi-jt.
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 freescale semiconductor 85 thermal 23.2.1 estimation of junction temperature with junction-to-ambient thermal resistance an estimation of the chip junction temperature, t j , can be obtained from the equation: t j = t a + ( r ja p d ) where: t j = junction temperature ( c) t a = ambient temperature for the package ( c) r ja = junction-to-ambient thermal resistance ( c/w) p d = power dissipation in the package (w) the junction-to-ambient thermal resistance is an i ndustry standard value that provides a quick and easy estimation of thermal performance. as a general statement, the value obtained on a single-layer board is appropriate for a tightly packed pr inted-circuit board. the value obtained on the board with the internal planes is usually appropriate if the board has low pow er dissipation and the components are well separated. test cases have demonstrated that errors of a factor of two (in the quantity t j ? t a ) are possible. 23.2.2 estimation of junction temperature with junction-to-board thermal resistance the thermal performance of a device cannot be adequately predicted from the junction-to-ambient thermal resistance. the thermal performance of any component is strongly dependent on the power dissipation of surrounding components. in addition, the ambient temper ature varies widely within the application. for many natural convection and especially closed box a pplications, the board temperature at the perimeter (edge) of the package will be approximately the same as the local air temperature near the device. specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that dete rmine the temperature of the device. at a known board temperature, the junction temperature is estimated using the following equation: t j = t b + ( r jb p d ) where: t j = junction temperature ( c) t b = board temperature at the package perimeter ( c) r ja = junction to board thermal resistance ( c/w) per jesd51-8 p d = power dissipation in the package (w) when the heat loss from the package case to the ai r can be ignored, acceptable predictions of junction temperature can be made. the application board shoul d be similar to the thermal test condition: the component is soldered to a board with internal planes.
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 86 freescale semiconductor thermal 23.2.3 experimental determination of junction temperature to determine the junction temperature of the device in the application after prototypes are available, the thermal characterization parameter ( jt ) can be used to determine the junction temperature with a measurement of the temperature at the top cente r of the package case using the following equation: t j = t t + ( jt p d ) where: t j = junction temperature ( c) t t = thermocouple temperature on top of package ( c) jt = junction-to-ambient thermal resistance ( c/w) p d = power dissipation in the package (w) the thermal characterization parameter is measured per jesd51-2 specification using a 40 gauge type t thermocouple epoxied to the top center of the package case. the thermocouple should be positioned so that the thermocouple junction rests on the packag e. a small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. the thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. 23.2.4 heat sinks and junction-to-ambient thermal resistance in some application environments, a heat sink will be required to provide the necessary thermal management of the device. when a heat sink is used, the thermal resistance is expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance: r ja = r jc + r ca where: r ja = junction-to-ambient thermal resistance ( c/w) r jc = junction-to-case thermal resistance ( c/w) r ca = case-to-ambient thermal resistance ( c/w) r jc is device related and cannot be influenced by the user. the user controls the thermal environment to change the case-to-ambient thermal resistance, r ca . for instance, the user can change the size of the heat sink, the airflow around the device, the interface mate rial, the mounting arrangement on printed-circuit board, or change the thermal dissipation on the printed-circuit board surrounding the device. to illustrate the thermal performance of the devices with heat sinks, the thermal performance has been simulated with a few commercially available heat sinks. the heat sink choice is determined by the application environment (temperature, airflow, adj acent component power dissipation) and the physical space available. because there is not a standard a pplication environment, a standard heat sink is not required.
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 freescale semiconductor 87 thermal table 76 shows heat sinks and junction-to-ambient thermal resistance for pbga package. accurate thermal design requires thermal modeling of the application environment using computational fluid dynamics software which can model both the c onduction cooling and the c onvection cooling of the air moving through the application. simplified thermal m odels of the packages can be assembled using the junction-to-case and junction-to-board thermal resistances listed in the thermal resistance table. more detailed thermal models can be made available on request. heat sink vendors include the following: aavid thermalloy 603-224-9988 80 commercial st. concord, nh 03301 internet: www.aavidthermalloy.com alpha novatech 408-749-7601 473 sapena ct. #15 santa clara, ca 95054 internet: www.alphanovatech.com international electronic research corporation (ierc) 818-842-7277 413 north moss st. burbank, ca 91502 internet: www.ctscorp.com table 76. heat sinks and junction-to-ambient thermal resistance of pbga package heat sink assuming thermal grease air flow 29 29 mm pbga thermal resistance aavid 30 30 9.4 mm pin fin natural convection 12.6 aavid 30 30 9.4 mm pin fin 1 m/s 8.2 aavid 30 30 9.4 mm pin fin 2 m/s 7.0 aavid 31 35 23 mm pin fin natural convection 10.5 aavid 31 35 23 mm pin fin 1 m/s 6.6 aavid 31 35 23 mm pin fin 2 m/s 6.1 wakefield, 53 53 25 mm pin fin natural convection 9.0 wakefield, 53 53 25 mm pin fin 1 m/s 5.6 wakefield, 53 53 25 mm pin fin 2 m/s 5.1 mei, 75 85 12 no adjacent board, extrusion natural convection 9.0 mei, 75 85 12 no adjacent board, extrusion 1 m/s 5.7 mei, 75 85 12 no adjacent board, extrusion 2 m/s 5.1
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 88 freescale semiconductor thermal millennium electronics (mei) 408-436-8770 loroco sites 671 east brokaw road san jose, ca 95112 internet: www.mei-millennium.com tyco electronics 800-522-6752 chip coolers? p.o. box 3668 harrisburg, pa 17105-3668 internet: www.chipcoolers.com wakefield engineering 603-635-5102 33 bridge st. pelham, nh 03076 internet: www.wakefield.com interface material vendors include the following: chomerics, inc. 781-935-4850 77 dragon ct. woburn, ma 01888-4014 internet: www.chomerics.com dow-corning corporation 800-248-2481 dow-corning electronic materials 2200 w. salzburg rd. midland, mi 48686-0997 internet: www.dowcorning.com shin-etsu microsi, inc. 888-642-7674 10028 s. 51st st. phoenix, az 85044 internet: www.microsi.com the bergquist company 800-347-4572 18930 west 78th st. chanhassen, mn 55317 internet: www.bergquistcompany.com 23.3 heat sink attachment when attaching heat sinks to these devices, an interface material is required. the best method is to use thermal grease and a spring clip. the spring clip should connect to the printed-circuit board, either to the board itself, to hooks soldered to the board, or to a plastic stiffener. avoid attachment forces which would lift the edge of the package or peel the package from the board. such peeling forces reduce the solder joint lifetime of the package. recommended maximum force on the top of the package is 10 lb force (4.5 kg force). if an adhesive attachment is planned, the a dhesive should be intended for attachment to painted or plastic surfaces and its performance verified under the application requirements.
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 freescale semiconductor 89 system design information 23.3.1 experimental determination of the junction temperature with a heat sink when heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material. a clearance slot or hole is normally required in the heat sink. minimizing the size of the clearance is important to minimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. because of the experimental difficulties with this technique, many engineers measure th e heat sink temperature and then back calculate the case temperature using a separate measurement of the thermal resistance of the interface. from this case temperature, the junction temperature is determined from the junction-to-case thermal resistance. t j = t c + ( r jc p d ) where: t j = junction temperature ( c) t c = case temperature of the package ( c) r jc = junction to case thermal resistance ( c/w) p d = power dissipation (w) 24 system design information this section provides electrical and thermal design recommendations for successful application of the mpc8358e. additional information can be found in mpc8360e/mpc8358e powerquicc design checklist (an3097). 24.1 system clocking the device includes two plls, as follows. ? the platform pll (av dd 1) generates the platform clock from the externally supplied clkin input. the frequency ratio between the platform and clkin is selected using the platform pll ratio configuration bits as described in section 22.1, ?system pll configuration.? ? the e300 core pll (av dd 2) generates the core clock as a slave to the platform clock. the frequency ratio between the e300 core clock and th e platform clock is selected using the e300 pll ratio configuration bits as described in section 22.2, ?core pll configuration.? 24.2 pll power supply filtering each of the plls listed above is provided with power through independent power supply pins (av dd 1, av dd 2, respectively). the av dd level should always be equivalent to v dd , and preferably these voltages will be derived directly from v dd through a low frequency filter scheme such as the following. there are a number of ways to reliably provide power to the plls, but the recommended solution is to provide five independent filter circuits as illustrated in figure 54 , one to each of the five av dd pins. by providing independent filters to each pll, the opportunity to cause noise injection from one pll to the other is reduced.
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 90 freescale semiconductor system design information this circuit is intended to filter noise in the p lls resonant frequency range from a 500 khz to 10 mhz range. it should be built with surface mount capacitor s with minimum effective series inductance (esl). consistent with the recommendations of dr. howard johnson in high speed digital design: a handbook of black magic (prentice hall, 1993), multiple small capacito rs of equal value are recommended over a single large value capacitor. each circuit should be placed as cl ose as possible to the specific av dd pin being supplied to minimize noise coupled from nearby circuits. it should be possible to route directly from the capacitors to the av dd pin, which is on the periphery of pack age, without the inductance of vias. figure 54 shows the pll power supply filter circuit. figure 54. pll power supply filter circuit 24.3 decoupling recommendations due to large address and data buses as well as high ope rating frequencies, the device can generate transient power surges and high frequency noise in its power suppl y, especially while driving large capacitive loads. this noise must be prevented from reaching other co mponents in the device system, and the device itself requires a clean, tightly regulated source of power. th erefore, it is recommended that the system designer place at least one decoupling capacitor at each v dd , ov dd , gv dd , and lv dd pins of the device. these decoupling capacitors should receive their power from separate v dd , ov dd , gv dd , lv dd , and gnd power planes in the pcb, utilizing short traces to min imize inductance. capacitors may be placed directly under the device using a standard escape pattern. others may surround the part. these capacitors should have a value of 0.01 or 0.1 f. only ceramic smt (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes. in addition, it is recommended that there be several bulk storage capacitors distributed around the pcb, feeding the v dd , ov dd , gv dd , and lv dd planes, to enable quick recharging of the smaller chip capacitors. these bulk capacitors should have a low esr (equivalent series resistance) rating to ensure the quick response time necessary. they should also be connected to the power and ground planes through two vias to minimize inductance. suggested bulk capacitors?100?330 f (avx tps tantalum or sanyo oscon). 24.4 connection recommendations to ensure reliable operation, it is highly recommende d to connect unused inputs to an appropriate signal level. unused active low inputs should be tied to ov dd , gv dd , or lv dd as required. unused active high inputs should be connected to gnd. all nc (no-connect) signals must remain unconnected. power and ground connections must be made to all external v dd , gv dd , lv dd , ov dd , and gnd pins of the device. v dd av dd n 2.2 f 2.2 f gnd low esl surface mount capacitors 10
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 freescale semiconductor 91 system design information 24.5 output buffer dc impedance the device drivers are characterized over process, voltage, and temperature. for all buses, the driver is a push-pull single-ended driver type (open drain for i 2 c). to measure z 0 for the single-ended drivers, an external resistor is connected from the chip pad to ov dd or gnd. then, the value of each resistor is varied until the pad voltage is ov dd /2 (see figure 55 ). the output impedance is the average of two components, the resistances of the pull-up and pull-down devices. when data is held high, sw1 is closed (sw2 is open) and r p is trimmed until the voltage at the pad equals ov dd /2. r p then becomes the resistance of the pull-up devices. r p and r n are designed to be close to each other in value. then, z 0 = (r p + r n )/2. figure 55. driver impedance measurement the value of this resistance and the strength of the driver?s current source can be found by making two measurements. first, the output voltage is measured while driving logic 1 without an external differential termination resistor. the measured voltage is v 1 = r source i source . second, the output voltage is measured while driving logic 1 with an external precision differential termination resistor of value r term . the measured voltage is v 2 = 1/(1/r 1 +1/r 2 )) i source . solving for the output impedance gives r source = r term (v 1 /v 2 ? 1). the drive current is then i source =v 1 /r source . table 77 summarizes the signal impedance targets. the driver impedance are targeted at minimum v dd , nominal ov dd , 105 c. table 77. impedance characteristics impedance local bus, ethernet, duart, control, configuration, power management pci ddr dram symbol unit r n 42 target 25 target 20 target z 0 w r p 42 target 25 target 20 target z 0 w ov dd ognd r p r n pad data sw1 sw2
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 92 freescale semiconductor ordering information 24.6 configuration pin muxing the device provides the user with power-on configuration options that can be set through the use of external pull-up or pull-down resistors of 4.7 k on certain output pins (see cu stomer visible configuration pins). these pins are generally used as output only pins in normal operation. while hreset is asserted however, these pins are treated as inputs. the value presented on these pins while hreset is asserted, is latched when hreset deasserts, at which time the input receiver is disabled and the i/o circuit takes on its normal function. care ful board layout with stubless connections to these pull-up/pull-down resistors coupled with the large value of the pull-up/pull-down resistor should minimize the disruption of signal quality or speed for output pins thus configured. 24.7 pull-up resistor requirements the device requires high resistance pull-up resistors (10 k is recommended) on open drain type pins including i 2 c pins, ethernet management mdio pin, and epic interrupt pins. for more information on required pull-up resistors and the connections required for the jtag interface, see mpc8360e/mpc8358e powerquicc design checklist (an3097). 25 ordering information 25.1 part numbers fully addressed by this document table 78 provides the freescale part numbering nomenclat ure for the mpc8358e. note that the individual part numbers correspond to a maximum processor core frequency. for available fr equencies, contact your local freescale sales office. in addition to the processor frequency, the part numbering scheme also differential na na na z diff w note: nominal supply voltages. see table 1 , t j = 105 c. table 77. impedance characteristics (continued) impedance local bus, ethernet, duart, control, configuration, power management pci ddr dram symbol unit
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 freescale semiconductor 93 ordering information includes an application modifier, which may specify sp ecial application conditions . each part number also contains a revision code that refers to the die mask revision number. table 79 shows the svr settings by device and package type. table 78. part numbering nomenclature 1 1 not all processor, platform, and quicc engine block frequency combinations are supported. for available frequency combinations, contact your local freescale sales office or authorized distributor. mpc nnnn e t pp aa a a a product code part identifier encryption acceleration temperature range package 2 2 see section 21, ?package and pin listings,? for more information on available package types. processor frequency 3 3 processor core frequencies supported by parts addressed by this specification only. not all parts described in this specificati on support all core frequencies. additionally, parts addressed by part number specifications may support other maximum core frequencies. platform frequency quicc engine frequency die revision mpc 8358 blank = not included e = included blank = 0 c t a to 105 c t j c= ?40 c t a to 105 c t j zq = pbga vr = pbga (no lead) e300 core speed ad = 266 mhz ag = 400 mhz d = 266 mhz d = 266 mhz g = 400 mhz a = revision 2.1 silicon table 79. svr settings device package svr (rev. 2.1) mpc8358e pbga 0x804e_0021 mpc8358 pbga 0x804f_0021
mpc8358e powerquicc ii pro processor revision 2.1 pbga silicon hardware specifications, rev. 3 94 freescale semiconductor document revision history 26 document revision history table 80 provides a revision history for this hardware specification. table 80. revision history rev. number date substantive change(s) 3 01/2011 ? updated references to the lcrr register throughout ? removed references to ddr dll mode in section 6.2.2, ?ddr and ddr2 sdram output ac timing specifications .? ? changed ?junction-to-case? to ?junction-to-ambient? in section 23.2.4, ?heat sinks and junction-to-ambient thermal resistance ,? and ta b l e 7 6 , ?heat sinks and junction-to-ambient thermal resistance of pbga package,? titles. 2 03/2010 ? changed references to rcwh[pcicken] to rcwh[pcickdrv]. ?in tab le 2 , added extended temperature characteristics. ? added figure 5 , ?ddr input timing diagram.? ? in figure 52 , ?mechanical dimensions and bottom surface nomenclature of the pbga package,? removed watermark. ?in tab le 4 , ?mpc8358e pbga core power dissipation 1 ,? added row for 400/266/400 part offering. ? updated the title of ta ble 1 8 ,?ddr sdram input ac timing specifications.? ?in tab le 1 9 , ?ddr and ddr2 sdram input ac timing specifications mode,? changed table subtitle. ?in ta b l e 2 6 ? ta b l e 2 9 , and ta ble 3 2 ? ta ble 3 3 , changed the rise and fall time specifications to reference 20?80% and 80?20% of the voltage supply, respectively. ?in table 37, ?ieee 1588 timer ac specifications,? changed first parameter to ?timer clock frequency.? ?in tab le 4 4 , ?i2c ac electrical specifications,? changed units to ?ns? for t i2dvkh . ?in table 65 ? mpc8358e pbga pinout listing, added note 7: ?this pin must always be tied to gnd? to the test pin. ?in tab le 6 7 , ?operating frequencies for the pbga package,? and table 78 , ?part numbering nomenclature,? updated for 400 mhz qe part offering ?in section 4, ?clock input timing ,? added note regarding rise/fall time on quicc engine block input pins. ? added section 4.3, ?gigabit reference clock input timing .? ? updated section 8.1.1, ?10/100/1000 ethernet dc electrical characteristics .? ?in section 21.3, ?pinout listings ,? added sentence stating ?refer to an3097, ?mpc8360/mpc8358e powerquicc design checklist,? for proper pin termination and usage.? ?in section 22, ?clocking ,? removed statement: ?the occr[pcicdn] parameters select whether clkin or clkin/2 is driven out on the pci_clk_outn signals.? ?in section 22.1, ?system pll configuration ,? updated the system vco frequency conditions. ?in tab le 7 8 , added extended temperature characteristics. 1 12/2007 initial release.
document number: mpc8358eec rev. 3 01/2011 information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center 1-800 441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconductor @hibbertgroup.com freescale, the freescale logo, and powerquicc are trademarks of freescale semiconductor, inc. reg. u.s. pat. & tm. off. quicc engine is a trademark of freescale semiconductor, inc. all other product or service names are the property of their respective owners. the power architecture and power.org word marks and the power and power.org logos and related marks are trademarks and service marks licensed by power.org. ? 2011 freescale semiconductor, inc.

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